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參數(shù)資料
| 型號(hào)： | MX98742 |
| 英文描述： | FEBC 100 Base Fast Ethernet Bridge Controller |
| 中文描述： | FEBC 100基地快速以太網(wǎng)橋控制器 |
| 文件頁(yè)數(shù)： | 15/36頁(yè) |
| 文件大?。?/td> | 166K |
| 代理商： | MX98742 |
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15
MX98745
P/N:PM0427
REV. 1.4, JUL. 8, 1998
D. Scrambler Control Register (register #17) (R/W)
Bit(s)
17.15:8
Name
Reserved
Description
Write any value to these bits have no effect.
Written value will be released onto MDIO
whenever Read Command is issued
1 : Enable Scrambler/Descrambler at Port 7
0 : Disable Scrambler/Descrambler at Port 7
The default value after power on is 1.
1 : Enable Scrambler/Descrambler at Port 6
0 : Disable Scrambler/Descrambler at Port 6
The default value after power on is 1.
1 : Enable Scrambler/Descrambler at Port 5
0 : Disable Scrambler/Descrambler at Port 5
The default value after power on is 1.
1 : Enable Scrambler/Descrambler at Port 4
0 : Disable Scrambler/Descrambler at Port 4
The default value after power on is 1.
1 : Enable Scrambler/Descrambler at Port 3
0 : Disable Scrambler/Descrambler at Port 3
The default value after power on is 1.
1 : Enable Scrambler/Descrambler at Port 2
0 : Disable Scrambler/Descrambler at Port 2
The default value after power on is 1.
1 : Enable Scrambler/Descrambler at Port 1
0 : Disable Scrambler/Descrambler at Port 1
The default value after power on is 1.
1 : Enable Scrambler/Descrambler at Port 0
0 : Disable Scrambler/Descrambler at Port 0
The default value after power on is 1.
R/W
R/W
17.7
ScrenP7
R/W
17.6
ScrenP6
R/W
17.5
ScrenP5
R/W
17.4
ScrenP4
R/W
17.3
ScrenP3
R/W
17.2
ScrenP2
R/W
17.1
ScrenP1
R/W
17.0
ScrenP0
R/W
Table 6-4 Scrambler Control Register Bit Definition
Note : When SCRCTRL is set to 0, contents of this regis-
ter will be disabled.
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