參數資料
型號: MX98742
英文描述: FEBC 100 Base Fast Ethernet Bridge Controller
中文描述: FEBC 100基地快速以太網橋控制器
文件頁數: 4/36頁
文件大小: 166K
代理商: MX98742
4
MX98745
P/N:PM0427
REV. 1.4, JUL. 8, 1998
5.0 PIN DESCRIPTION
A. MX Data Transceiver (Am78965/Am78966 or MC68836), 98 pins
PAD #
24-28
9-13
155-159
142-146
128-132
113-117
98-102
30
Name
TDAT[7:1][0:4]
I/O
O,
TTL
Description
Transmit Data. These five outputs are 5B encoded transmit data sym
bols, driven at the rising edge of LSCLK.
TDAT4 is the Most Significant Bit.
LSCLK
I,
TTL
Local Synchrnous Clock. This pin supplies the frequency reference to
the MX98745 within same HUB. It should be driven by a crystal-
controlled 25M clock source.
Receive Data. These 5 bit parallel data symbol from transceiver are
latched by the rising edge of RSCLK of each port.
RDAT4 is the Most Significant Bit.
18-22
4-8
150-154
137-141
122-126
107-111
92-96
15,2
148,134
118,104
90,42
16,3,
149,135,
119,105,
91
31
RDAT[7:1][0:4]
I,
TTL
RSCLK[7:0]
I,
TTL
Recovered Symbol Clock. This is a 25 MHz clock, which is derived
from the clock synchronization PLL circuit.
SIGDET[7:1]
I,
TTL
Signal Detect. This signal indicates that the received signal is above
the detection threshold and will be used for the link test state machine.
Monitor
I,
TTL
Monitor Mode. Internal Pulldown. When this pin is set to one, LED
display pins LED[9:0] will be changed to monitor mode.
Table 5-1 Pin Description for XRCII
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MX98748 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Highly Intergated 10/100M Dual Speed Hub With Extra 4 Port Switch Built-In