參數(shù)資料
型號: MT90871AV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 8K Digital Switch (F8KDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA196
封裝: 15 X 15 MM, 1 MM PITCH, LBGA-196
文件頁數(shù): 6/65頁
文件大?。?/td> 639K
代理商: MT90871AV
MT90871
Data Sheet
6
Zarlink Semiconductor Inc.
LSTi0-15
K14, J13, J14, K13,
M14, J12, L14,
M13, L13, N14,
M12, N12, N13,
M11, L12, K12
Local Serial Input Streams 0 to 15 (5V Tolerant with internal pull-
down).
These pins accept serial TDM data streams at a data-rate of:
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048Mb/s (with 32 channels per stream).
The data-rate is independently programmable for each input stream.
C16o Output Clock (Three-state Output).
A 16.384MHz clock output.
The clock falling edge or rising edge is aligned with the Local
frame boundary, and is determined by the COPOL bit of the Control
Register.
C8o Output Clock (Three-state Output).
A 8.192MHz clock output. The
clock falling edge or rising edge is aligned with the Local frame boundary,
and is determined by the COPOL bit of the Control Register.
Frame Pulse Output (Three-state Output).
Frame pulse output is active
for 61ns at the frame boundary. The frame pulse, running at a 8KHz rate,
will be the same format (ST-BUS or GCI-BUS) as the input frame pulse
(FP8i).
Frame Pulse Output (Three-state Output).
Frame pulse output is active
for 122ns at the frame boundary. The frame pulse, running at 8KHz rate,
will be the same style (ST-BUS or GCI-BUS) as the input frame pulse
(FP8i).
Local Serial Output Streams 0 to 15 (5V Tolerant Three-state
Outputs).
These pins output serial TDM data streams at a data-rate of:
16.384 Mb/s (with 256 channels per stream),
8.192 Mb/s (with 128 channels per stream),
4.096 Mb/s (with 64 channels per stream), or
2.048Mb/s (with 32 channels per stream).
C16o
M9
C8o
N10
FP16o
P12
FP8o
N11
LSTo0 - 15
B13, B14, D14,
C14, D12, E14,
D13, E13, E12,
F14, G14, G12,
F12, F13, H14,
G13
The data-rate is independently programmable for each output stream.
Refer to descriptions of the
LORS
and
ODE
pins for control of the output
High or High-Impedance state.
Local Output Channel High Impedance Control (5V Tolerant Three-state
Outputs).
Active high output enable which may be used to control external buffering
individually for a set of Local output streams on a per channel basis.
LCSTo0-1
C12, B12
LCSTo0 is the output enable for LSTo[0, 2, 4, 6, 8, 10, 12, 14],
LCSTo1 is the output enable for LSTo[1, 3, 5, 7, 9, 11, 13, 15].
Refer to descriptions of the
LORS
and
ODE
pins for control of the output
High or High-Impedance state.
Pin Description Table (continued)
Name
Package
Coordinates
Description
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