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參數(shù)資料
| 型號： | MT90871AV |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | Flexible 8K Digital Switch (F8KDX) |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA196 |
| 封裝： | 15 X 15 MM, 1 MM PITCH, LBGA-196 |
| 文件頁數(shù)： | 26/65頁 |
| 文件大?。?/td> | 639K |
| 代理商： | MT90871AV |
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MT90871
Data Sheet
26
Zarlink Semiconductor Inc.
The Control Register bits MS2, MS1, and MS0 must be set to 000, respectively, to select the Local Connection
Memory for the Write and Read operations via the microprocessor port. See Section 7.0 "Microprocessor
Port", and Section 13.1 "Control Register (CR)" for details on microprocessor port access.
6.2
Backplane Connection Memory
The Backplane Connection Memory (BCM) is 16-bit wide with 4,096 memory locations to support the
Backplane output port. The most significant bit of each word, bit [15], selects the source stream from either the
Backplane or the Local port and determines the Local-to-Backplane or Backplane-to-Backplane data routing.
Bits [14:13] select the control modes of the Backplane output streams, namely the per-channel Message Mode
and the per-channel high impedance output control mode. In Connection Mode (Bit14 = LOW), Bits [12:0]
select the source stream and channel number as detailed in Table 4. In Message Mode (Bit14 = HIGH), Bits
[12:8] are unused and Bits [7:0] contain the message byte to be transmitted.
The Control Register bits MS2, MS1, and MS0 must be set to 001, respectively, to select the Backplane
Connection Memory for the Write and Read operations via the microprocessor port. See Section 7.0, and
Section 13.1
.
6.3
Connection Memory Block Programming
This feature allows fast simultaneous initialization of the Local and Backplane Connection Memories after
power up. When the Memory Block Programming mode is enabled, the contents of the Block Programming
Register (BPR) will be loaded into the connection memories. See Table 13 and Table 14 for details of the
Control Register and Block Programming Register values, respectively.
6.3.1
Memory Block Programming Procedure
Set the
MBP
bit in the Control Register from LOW to HIGH.
Set the
BPE
bit to HIGH in the Block Programming Register (BPR). The Local Block Programming data bits,
LBPD2-0
, of the Block Programming Register, will be loaded into Bit 15, Bit 14 and Bit 13, respectively, of
the Local Connection Memory. The remaining bit positions are loaded with zeros as shown in Table 5.
Table 5- Local Connection Memory in Block Programming Mode
The Backplane Block Programming data bits,
BBPD2-0
, of the Block Programming Register, will be loaded into
Bit 15, Bit 14 and Bit 13, respectively, of the Backplane Connection Memory. The remaining bit positions are
loaded with zeros as shown in Table 6.
Source Stream Bit Rate
Source Stream No.
Source Channel No.
2Mb/s
[12:8]
legal values 0 - 15
[7:0]
legal values 0 - 31
4Mb/s
[12:8]
legal values 0 - 15
[7:0]
legal values 0 - 63
8Mb/s
[12:8]
legal values 0 - 15
[7:0]
legal values 0 - 127
16Mb/s
[12:8]
legal values 0 - 15
[7:0]
legal values 0 - 255
Table 4- Local and Backplane Connection Memory Configuration
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LBPD2
LBPD1
LBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
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| MT90871 | Flexible 8K Digital Switch (F8KDX) |
| MT90883 | TDM to Packet Processors |
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90871AV2 | 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA |
| MT90880 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880B/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90880BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
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