參數(shù)資料
型號(hào): MT90871AV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類(lèi): 路由/交換
英文描述: Flexible 8K Digital Switch (F8KDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA196
封裝: 15 X 15 MM, 1 MM PITCH, LBGA-196
文件頁(yè)數(shù): 48/65頁(yè)
文件大小: 639K
代理商: MT90871AV
MT90871
Data Sheet
48
Zarlink Semiconductor Inc.
13.10.4
Backplane BER Start Receive Register (BBSRR)
Address 00CBh
Backplane BER Start Receive Register defines the Input Stream and the Start Channel in which the BER sequence
shall be received. The
BBSRR
register is configured as follows:
13.10.5
Backplane BER Count Register (BBCR)
Address 00CCh
Backplane BER Count Register contains the number of counted errors. This register is read only. The
BBCR
register is configured as follows:
13.11
Local Bit Rate Registers
13.11.1
Local Input Bit Rate Registers (LIBRR0-15)
Address 00CDh to 00DCh.
Sixteen Local Input Bit Rate Registers allow the bit rate for each individual stream to be set to 2, 4, 8 or
16 Mb/s. The
LIBRR
registers are configured as follows:
Bit
Name
Reset
Description
15-13
Reserved
0
Reserved.
12-9
BBRSA(3:0)
0
Backplane BER Receive Stream Address Bits
The binary value of these bits defines the Backplane input stream that
receives the BER data.
8-0
BBRCA(8:0)
0
Backplane BER Receive Channel Address Bits
The binary value of these bits define the Backplane input Start Channel in
which the BER data will be received.
Table 36- Backplane BER Start Receive Register (BBSRR) Bits
Bit
Name
Reset
Description
15-0
BBC(15:0)
0
Backplane Bit Error Rate Count
The binary value of these bits define the Backplane Bit Error count.
Table 37- Backplane BER Count Register (BBCR) Bits
LIBRn
(for n=0 to 15)
Name
Reset
Description
15-2
Reserved
0
Reserved
1-0
LIBR(1:0)
0
Local Input Bit Rate
Table 38- Local Input Bit Rate Register (LIBRRn) Bits
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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MT90880B 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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MT90880BP1N 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors