參數資料
型號： MT90871AV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 8K Digital Switch (F8KDX)
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA196
封裝： 15 X 15 MM, 1 MM PITCH, LBGA-196
文件頁數： 27/65頁
文件大?。?/td> 639K
代理商： MT90871AV
Data Sheet
MT90871
27
Zarlink Semiconductor Inc.
Table 6- Backplane Connection Memory in Block Programming Mode
The Block Programming Register bit, BPE will be automatically reset LOW within 125us, to indicate completion
of memory programming.
The Block Programming Mode can be terminated at any time prior to completion by setting the
BPE
bit of the
Block Programming Register or the MBP bit of the Control Register to LOW.
Note the default values (LOW) of
LBPD2-0
and
BBPD2-0
of the Block Programming Register, following a
device reset, may be used. These settings shall set all output channels to High, or High-Impedance, in
accordance with the
LORS
and
BORS
pin conditions, see Pin Description for further details. The Local
Connection Memory shall be configured to select data from Channel 0 of Backplane input Stream 0 (
BSTi0
),
and the Backplane Connection Memory shall be configured to select data from Channel 0 of Local input
Stream 0 (
LSTi0
). Alternative conditions may be established by programming bits
LBPD2-0
and
BBPD2-0
of
the Block Programming Register at the time of setting Bit
BPE
to HIGH. See section 12.3 "Local Connection
Memory Bit Definition", section 12.4 "Backplane Connection Memory Bit Definition", and section 13.2 "Block
Programming Register (BPR)".
7.0
Microprocessor Port
The MT90871 supports non-multiplexed Motorola microprocessors. The microprocessor port consists of 16-bit
parallel data bus (
D0-15
), 15-bit address bus (
A0-14
) and four control signals (
CS, DS, R/W
and
DTA
). The
data bus provides access to the internal registers, the Backplane Connection and Data memories, and the
Local Connection and Data memories. Each memory has 4,096 locations. See Table 7, Address Map for Data
and Connection Memory Locations (A14=1), for the address mapping.
Each Connection Memory can be read or written via the 16-bit microprocessor port. The Data Memories can
only be read (but not written) from the microprocessor port.
To prevent the bus ’hanging’, in the event of the MT90871 not receiving a master clock, the microprocessor
port shall complete the DTA handshake when accessed but any data read from the bus will be invalid.
There must be a minimum of 30ns between CPU accesses, to allow the MT90869 device to recognize the
accesses as separate (i.e. a minimum of 30ns must separate the de-assertion of DTA_b (to high) and the
assertion of CS_b and/or DS_6 to initiate the next access).
8.0
Device Power-up, Initialization and Reset
8.1
Power-Up Sequence
The recommended power-up sequence is for the VDD_IO supply (nominally +3.3V) to be established before
the power-up of the VDD_PLL and VDD_CORE supplies (nominally +1.8V). The VDD_PLL and VDD_CORE
supplies may be powered up simultaneously, but neither should 'lead' the VDD_IO supply by more than 0.3V.
All supplies may be powered-down simultaneously.
8.2
Initialization
Upon power up, the MT90871 should be initialized by applying the following sequence:
1.
2.
Ensure the
TRST
pin is permenantly LOW to disable the JTAG TAP controller.
Set
ODE
pin to LOW. This configures the
LCSTo0-1
output signals to LOW (i.e. to set optional external
output buffers to high impedance), and sets the
LSTo0-15
outputs to high or high impedance, dependent
on the
LORS
input value, and sets the
BCSTo0-1
output signals
to
LOW (i.e. to set optional external
output buffers to high impedance), and sets the
BSTo0-15
outputs to high or high impedance, dependent
on
BORS
input value. Refer to Pin Description for details of the
LORS
and
BORS
pins.
Reset the device by pulsing the
RESET
pin to zero for at least two cycles of the input clock,
C8i
.
3.
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
BBPD2
BBPD1
BBPD0
0
0
0
0
0
0
0
0
0
0
0
0
0
相關PDF資料
PDF描述
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相關代理商/技術參數
參數描述
MT90871AV2 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
MT90880 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880BP1N 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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