參數(shù)資料
型號： MT90871AV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 8K Digital Switch (F8KDX)
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA196
封裝： 15 X 15 MM, 1 MM PITCH, LBGA-196
文件頁數(shù)： 18/65頁
文件大?。?/td> 639K
代理商： MT90871AV
MT90871
Data Sheet
18
Zarlink Semiconductor Inc.
2.
The Channel Control Bit corresponding to Stream 14, Channel 0,
LSTo14_Ch0,
is transmitted on
LCSTo0
in advance of the Frame Boundary by three periods of output clock,
C16o
. Similarly, the
Channel Control Bit for
LSTo15_Ch0
is advanced relative to the Frame Boundary by three periods of
C16o
, on
LCSTo1
.
The
LCSTo0-1
outputs data at a constant data-rate of 16.384Mb/s, independent of the data-rate selected for
the individual output streams,
LSTo0-15
. Streams at data-rates lower than 16.384Mb/s will have the value of
the respective channel control bit repeated for the duration of the channel. The bit will be transmitted twice for
8.192Mb/s streams, four times for 4.096Mb/s streams and eight times for 2.048Mb/s streams. The channel
control bit is not repeated for 16.384Mb/s streams.
Examples are presented, with reference to Table 2:
3.
With stream
LSTo2
selected to operate at a data-rate of 2.048Mb/s, the value of the Channel Control Bit
for
Channel 0
will be transmitted during the
C16o
clock period nos. 2040, 2048, 8, 16, 24, 32, 40 and 48.
With stream
LSTo4
operated at a data-rate of 8.192Mb/s, the value of the Channel Control Bit for
Channel 1
will be transmitted during the
C16o
clock period nos. 9 and 17.
Figure 13, Local Port External High Impedance Control Bit Timing (ST-Bus mode) shows the channel control
bits for
LCSTo0
and
LCSTo1
in one possible scenario which includes stream
LSTo0
at a data-rate of
16.384Mb/s,
LSTo1
at 8.192Mb/s,
LSTo6
at 4.096Mb/s and
LSTo7
at 2.048Mb/s. All remaining streams are
operated at a data-rate of 16.384Mb/s.
4.
4.1.2
LORS Set HIGH
The Local Output Enable Bit (
LE
) of the Local Connection Memory has direct per-channel control on the high-
impedance state of the Local Output streams,
LSTo0-15
. Programming a LOW state will set the stream output
of the MT90871 to High Impedance for the duration of the channel period. See section 12.3 "Local Connection
Memory Bit Definition", for programming details.
The
LCSTo0-1
outputs remain active.
Allocated
Stream No.
Allocated Channel No.
2
C16o
Period
1
LCSTo0
LCSTo1
16Mb/s
8Mb/s
4Mb/s
2Mb/s
2039
0
3-1
1
Ch 0
Ch 0
Ch 0
Ch 0
2040
2
3-3
3
Ch 0
Ch 0
Ch 0
Ch 0
2041
4
5
Ch 0
Ch 0
Ch 0
Ch 0
2042
6
7
Ch 0
Ch 0
Ch 0
Ch 0
2043
8
9
Ch 0
Ch 0
Ch 0
Ch 0
2044
10
11
Ch 0
Ch 0
Ch 0
Ch 0
2045
12
13
Ch 0
Ch 0
Ch 0
Ch 0
2046
14
3-2
15
3-2
Ch 0
Ch 0
Ch 0
Ch 0
2047
0
1
Ch 1
Ch 0
Ch 0
Ch 0
2048
2
3-3
3
Ch 1
Ch 0
Ch 0
Ch 0
Frame
1
4
5
Ch 1
Ch 0
Ch 0
Ch 0
Boundary
2
6
7
Ch 1
Ch 0
Ch 0
Ch 0
3
8
9
Ch 1
Ch 0
Ch 0
Ch 0
4
10
11
Ch 1
Ch 0
Ch 0
Ch 0
Table 2- LCSTo Allocation of Channel Control Bits to the Output Streams
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