參數(shù)資料
型號(hào)： MT90871AV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 8K Digital Switch (F8KDX)
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA196
封裝： 15 X 15 MM, 1 MM PITCH, LBGA-196
文件頁(yè)數(shù)： 28/65頁(yè)
文件大?。?/td> 639K
代理商： MT90871AV
MT90871
Data Sheet
28
Zarlink Semiconductor Inc.
4.
Use the Block Programming Mode to initialize the Local and the Backplane Connection Memories. Refer
to 6.3 "Connection Memory Block Programming".
Set
ODE
pin to HIGH after the connection memories are programmed to ensure that bus contention will
not occur at the serial stream outputs.
5.
8.3
Reset
The
RESET
pin is used to reset the device. When set LOW, an asynchronous reset is applied to the MT90871.
It is synchronized to the internal clock and remains active for 50 us following release (set HIGH) of the external
RESET
to allow time for the PLL to fully settle. During the reset period, depending on the state of input pins
LORS
and
BORS
, the output streams
LSTo0- 15
and
BSTo0-15
are set to high or high impedance, and all
internal registers and counters are reset to the default state.
The
RESET
pin must remain low for two input clock cycles (
C8i
) to guarantee a synchronized reset release.
When
RESET
is applied to the MT90871, the
CS
line is inhibited and the
DTA
line may become active through
simultaneous microport activity. External gating of the
DTA
line with
CS
is recommended to avoid bus conflict
in applications incorporating multiple devices with individual reset conditions.
9.0
Bit Error Rate Test
Independent Bit Error Rate (BER) test mechanisms are provided for the Local and Backplane ports. In both
ports there is a BER transmitter and a BER receiver. The transmitter and receiver are each independently
controlled to allow either looped back or uni-directional testing. The transmitter generates a 2
15
-1 or 2
23
-1
Pseudo Random Binary Sequence (PRBS), which may be allocated to a specific stream and a number of
channels. This is defined by a stream number, a start channel number, and the number of consecutive
channels following the start channel. The stream, channel number and the number of consecutive channels
following the start channel are similarly allocated for the receiver and detection of the PRBS. Examples of a
channel sequence are presented in Figure 16.
When enabled, the receiver attempts to lock to the PRBS on the incoming bit stream. Once lock is achieved by
detection of a seed value, a bit by bit comparison takes place and each error shall increment a 16-bit counter.
A counter ’roll-over’ shall occur in the event of an error count in excess of 65535.
The BER operations are controlled by registers as follows
(refer to section 13.3 "Bit Error Rate Test Control
Register (BERCR)"
for overall control,
section 13.9.2 "Local Bit Error Rate (BER) Registers"
and section 13.10
"Backplane Bit Error Rate (BER) Registers" for register programming details):
BER Control Register (
BERCR
) - Independently enables BER transmission and receive testing for
Backplane and Local ports.
Local and Backplane BER Start Send Registers (
LBSSR
and
BBSSR
) - Defines the output stream and start
channel for BER transmission.
Local and Backplane Transmit BER Length Registers (
LTXBLR
and
BTXBLR
) - Defines, for transmit
stream, how many consecutive channels to follow the start channel.
Local and Backplane BER Start Receive Registers (
LBSR
and
BBSR
) - Define the input stream and
channel from where the BER sequence will start to be compared.
Local and Backplane Receive BER Length Registers (
LRXBLR
and
BRXBLR
) - Defines, for the receive
stream, how many consecutive channels follow the start channel.
Local and Backplane BER Count Registers (
LBCR
and
BBCR
) - Contain the number of counted errors.
The registers listed completely define the transmit stream and channels. When BER transmission is enabled
for these channels the source bits and the message mode bits,
LSRC
and
LMM
in the Local Connection
Memory, and
BSRC
and
BMM
in the Backplane Connection Memory are ignored. The enable bits (
LE
and
BE
)
of the respective connection memories should be set to HIGH to enable the outputs for the selected channels.
相關(guān)PDF資料
PDF描述
MT90871 Flexible 8K Digital Switch (F8KDX)
MT90883 TDM to Packet Processors
MT91600 Programmable SLIC
MT91600AN Programmable SLIC
MT91600AN1 Programmable SLIC
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90871AV2 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
MT90880 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880BP1N 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*