MT90871
Data Sheet
2
Zarlink Semiconductor Inc.
Per-channel message mode for Local and Backplane output streams.
Connection memory block programming for fast device initialization.
Automatic selection between ST-BUS and GCI-BUS operation.
Non-multiplexed Motorola microprocessor interface.
BER testing for Local and Backplane ports.
Conforms to the mandatory requirements of the IEEE-1149.1 (JTAG) standard.
Memory Built-In-Self-Test (BIST), controlled via microprocessor registers.
1.8V core supply voltage.
3.3V I/O supply voltage.
5V tolerant inputs, outputs and I/Os.
Per stream subrate switching at 4-bit, 2-bit, 1-bit depending on stream data rate.
Applications
Central Office Switches (Class 5)
Mediation Switches
Class-independent switches
Access Concentrators
Scalable TDM-Based Architectures
Digital Loop Carriers
Device Overview
The MT90871 has two data ports, the Backplane and the Local port. The Backplane port has 16 input and 16
output streams operated at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, in any combination and the Local
port has 16 input and 16 output streams operated at 2.048Mb/s, 4.096Mb/s, 8.192Mb/s or 16.384Mb/s, in any
combination.
The MT90871 contains two data memory blocks (Backplane and Local) to provide the following switching path
configurations:
Backplane-to-Local, supporting 4K x 4K data switching,
Local-to-Backplane, supporting 4K x 4K data switching,
Backplane-to-Backplane, supporting 4K x 4K data switching.
Local-to-Local, supporting 4K x 4K data switching.
The device contains two connection memory blocks, one for the Backplane output and one for the Local output. Data
to be output on the serial streams may come from either of the data memories (Connection Mode) or directly from
the connection memory contents (Message Mode).
In Connection Mode the contents of the connection memory defines, for each output stream and channel, the source
stream and channel (stored in data memory) to be switched.
In Message Mode, microprocessor data can be written to the connection memory for broadcast on the output
streams on a per channel basis. This feature is useful for transferring control and status information to external
circuits or other ST-BUS devices.
The device uses a master frame pulse (FP8i) and master clock (C8i) to define the frame boundary and timing for
both the Backplane port and the Local port. The device will automatically detect whether an ST-BUS or a GCI-BUS
style frame pulse is being used. There is a two frame delay from the time RESET is de-asserted to the establishment
of full switch functionality. During this period the frame format is determined before switching begins. The device
provides FP8o, FP16o, C8o and C16o outputs to support external devices connected to the Local port.
Subrate switching can be accomplished by over-sampling (i.e. 1-bit switching can be achieved by sampling a 2Mbps
stream at 16Mbps). Refer to MSAN-175.