參數資料
型號： MT90871AV
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： Flexible 8K Digital Switch (F8KDX)
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA196
封裝： 15 X 15 MM, 1 MM PITCH, LBGA-196
文件頁數： 37/65頁
文件大小： 639K
代理商： MT90871AV
Data Sheet
MT90871
37
Zarlink Semiconductor Inc.
When BPE is HIGH, no other bits of the BPR register must be changed for at least a single frame period, except
to abort the programming operation. The programming operation may be aborted by setting either BPE to LOW,
or the Control Register bit, MBP, to LOW.
The
BPR
register is configured as follows.
.
13.3
Bit Error Rate Test Control Register (BERCR)
Address 0002h.
The BER control register controls Backplane and Local port BER testing. It independently enables and
disables transmission and reception. It is configured as follows:
Bit
Name
Reset
Description
15-7
Unused
0
Set LOW
.
6-4
BBPD(2:0)
0
Backplane Block Programming Data.
These bits refer to the value loaded into the Backplane Connection Memory
(BCM) when the Memory Block Programming feature is activated. When the
MBP bit in the Control Register (CR) is set HIGH and the BPE is set HIGH, the
contents of Bits BBPD2-0 are loaded into Bits 15-13, respectively, of the BCM.
Bits 12-0 of the BCM are set LOW
3-1
LBPD(2:0)
0
Local block Programming Data.
These bits refer to the value loaded into the Local Connection Memory (LCM),
when the Memory Block Programming feature is activated. When the MBP bit in
the Control Register is set HIGH and the BPE is set HIGH, the contents of Bits
LBPD2-0 are loaded into Bits 15-13, respectively, of the LCM.
Bits 12-0 of the LCM are set LOW
0
BPE
0
Block Programming Enable.
A LOW to HIGH transition of this bit enables the Memory Block Programming
function. A LOW will be returned after 125us, upon completion of programming.
Set LOW to abort the programming operation.
Table 14- Block Programming Register Bits
Bit
Name
RESET
Description
15-12
Reserved
0
Reserved.
11
LOCKB
0
Backplane Lock (READ ONLY).
This bit is automatically set HIGH when the receiver has locked to the
incoming data sequence. The bit is reset by a LOW to HIGH transition on
SBERRXB.
10
PRSTB
0
PBER Reset for Backplane.
A LOW to HIGH transition initializes the Backplane BER generator to the
seed value.
9
CBERB
0
Clear Bit Error Rate Register for Backplane.
A LOW to HIGH transition in this bit resets the Backplane internal bit error
counter and the Backplane bit error (BBERR) register to zero.
Table 15- Bit Error Rate Test Control Register (BERCR) Bits
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相關代理商/技術參數
參數描述
MT90871AV2 制造商:Microsemi Corporation 功能描述:PB FREE FLEXIBLE 8K DIGITAL SWITCH - Bulk 制造商:Microsemi Corporation 功能描述:IC, TDM SWITCH 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH F8KDX 196PBGA 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH F8KDX 196PBGA
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MT90880B 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880B/IG 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
MT90880BP1N 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors
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