參數(shù)資料
型號(hào): MT90871AV
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: Flexible 8K Digital Switch (F8KDX)
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA196
封裝: 15 X 15 MM, 1 MM PITCH, LBGA-196
文件頁(yè)數(shù): 41/65頁(yè)
文件大?。?/td> 639K
代理商: MT90871AV
Data Sheet
MT90871
41
Zarlink Semiconductor Inc.
13.6
Backplane Input Channel Delay Registers (BCDR0 to BCDR15)
Address 0043h to 0052h
Sixteen Backplane input channel delay registers (BCDR0 to BCDR15) allow users to program the input channel
delay for the Backplane input data streams BSTi0-15. The possible adjustment is 255 channels and the
BCDR0 to
BCDR15
registers are configured as follows:
13.6.1
Backplane Channel Delay Bits 8-0 (BCDn8 - BCDn0)
These eight bits define the delay, in channel numbers, the serial interface receiver takes to store the channel data
from the Backplane stream input pins. The input channel delay can be set to 255 (16Mb/s streams), 127 (8Mb/s
streams), 63 (4Mb/s streams) or 31 (2Mb/s streams) from the frame boundary.
4 1/2
1
0
0
1
0
4 3/4
1
0
0
1
1
5
1
0
1
0
0
5 1/4
1
0
1
0
1
5 1/2
1
0
1
1
0
5 3/4
1
0
1
1
1
6
1
1
0
0
0
6 1/4
1
1
0
0
1
6 1/2
1
1
0
1
0
6 3/4
1
1
0
1
1
7
1
1
1
0
0
7 1/4
1
1
1
0
1
7 1/2
1
1
1
1
0
7 3/4
1
1
1
1
1
BCDRn Bit
(where n = 0 to 15 )
Name
Reset
Description
15-8
Reserved
0
Reserved
7-0
BCD(7:0)
0
Backplane Channel Delay Register
The binary value of these bits refers to the channel
delay value for the Backplane input stream
Table 20- Backplane Channel Delay Register (BCDRn) Bits
Corresponding Delay Bits
Data Rate
LID4
LID3
LID2
LID1
LID0
Table 19- Local Input Bit Delay Programming Table (continued)
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