參數(shù)資料
型號: MT9074
廠商: Mitel Networks Corporation
英文描述: T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
中文描述: T1/E1/J1收發(fā)單芯片收發(fā)器(T1/E1/J1收發(fā)單片收發(fā)器)
文件頁數(shù): 92/120頁
文件大小: 362K
代理商: MT9074
MT9074
Advance Information
92
Bit
Name
Functional Description
7
FERRO
Errored
Signal
Interrupt
. When unmasked this
interrupt bit goes high whenever
the errored frame alignment signal
counter changes from FFH to 00H.
Reading this register clears this
bit.
Framing
Counter
Alignment
Overflow
6
CRCO
CRC Error Counter Overflow
Interrupt
. When unmasked this
interrupt bit goes high whenever
the CRC error counter changes
from FFH to 00H. Reading this
register clears this bit.
5
FEBEO
E-bit
Interrupt
. When unmasked this
interrupt bit goes high whenever
the E-bit counter changes from
FFH to 00H. Reading this register
clears this bit.
Counter
Overflow
4
- - -
Unused
3
BPVO
Bipolar
Overflow
unmasked this interrupt bit goes
high whenever the bipolar violation
counter changes from FFH to 00H.
Reading this register clears this
bit.
Violation
Interrupt.
Counter
When
2
PRBSO
Pseudo Random Bit Sequence
Error
Counter
Interrupt
. When unmasked this
interrupt bit goes high whenever
the PRBS error counter changes
from FFH to 00H. Reading this
register clears this bit.
Overflow
1
PRBSMFO
Pseudo Random Bit Sequence
Multiframe Counter Overflow
Interrupt.
When unmasked this
interrupt bit goes high whenever
the multiframe counter attached to
the PRBS error counter overflows.
FFH to 00H. 1 - unmasked, 0 -
masked.
0
- - -
Unused
Table 128 - Interrupt Word Two
(Page 4, Address 1DH) (E1)
Bit
Name
Functional Description
7
- - -
Unused
6
HDLC0I
HDLC0 Interrupt.
Whenever an
unmasked HDLC0 interrupt occurs.
This bit goes high. Reading this
register clears this bit.
5
HDLC1I
HDLC1 Interrupt.
Whenever an
unmasked HDLC1 interrupt occurs.
this bit goes high. Reading this
register clears this bit.
4
JAI
Jitter Attenuator Error Interrupt
.
Whenever an unmasked JAI interrupt
occurs.
If jitter attenuator FIFO comes within
four bytes of an overflow or underflow,
this bit goes high. Reading this
register clears this bit.
3
1SECI
One Second Status Interrupt.
When
unmasked this interrupt bit goes high
whenever the 1SEC status bit (page 3
address 12H bit 7) goes from low to
high. Reading this register clears this
bit.
2
5SECI
Five Second Status Interrupt
. When
unmasked this interrupt bit goes high
whenever the 5 SEC status bit goes
from low to high. Reading this register
clears this bit.
1
RCRI
RCRI
unmasked RCRI interrupt occurs. If
remote alarm and CRC error occur
this bit goes high. Reading this
register clears this bit.
Interrupt.
Whenever
an
0
SIGI
Signalling
unmasked this interrupt bit goes high
whenever
a
change
(optionally debounced - see DBEn in
the Data Link, Signalling Control
Word) is detected in the signalling bits
(AB or ABCD) pattern. Reading this
register clears this bit.
Interrupt
.
When
of
state
Table 129 - Interrupt Word Three
(Page 4, Address 1EH) (E1)
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