參數(shù)資料
型號： MT9074
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器（T1/E1/J1收發(fā)單片收發(fā)器）
文件頁數(shù)： 52/120頁
文件大?。?/td> 362K
代理商： MT9074
MT9074
Advance Information
52
Bit
Name
Functional Description
7
T1/E1
T1/E1 mode selection.
when this
bit is zero, the device is in T1
mode. When set high, the device
is in E1 mode.
6-5
RSV
Reserved.
Must be kept at 0 for
normal operation.
4
LIUEn
LIU Enable.
Setting this bit low
enables the internal LIU front-end.
Setting this pin high disables the
LIU. Digital inputs RXA and RXB
are sampled by the rising edge of
E1.5i (C1.50) to strobe in the
received line data. Digital transmit
data is clocked out of pins TXA
and TXB with the rising edge of
C1.5o
3-2
RSV
Reserved.
Must be kept at 0 for
normal operation.
1
ADSEQ
Digital Milliwatt or Digital Test
Sequence
. If one, the Alaw digital
milliwatt analog test sequence will
be selected for those channels
with per time slot control bits
TTST, RRST set. If zero, a PRBS
generator / detector will be
connected to channels with TTST,
RRST respectively.
0
RSV
Reserved.
Must be kept at 0 for
normal operation.
Table 38 - Configuration Control Word
(Page 2, Address 10H) (T1)
Bit
Name
Functional Description
7
RSV
Reserved.
Must be kept high for
normal operation.
6-4
RSV
Reserved.
Must be kept low for normal
operation.
3
CPL
Custom Pulse Level.
Setting this bit
low enables the internal ROM values in
generating the transmit pulses. The
ROM is coded for different line
terminations or build out, as specified
in the LIU Control word. Setting this bit
high disables the pre-programmed
pulse templates. Each of the 4 phases
that generate a mark derive their D/A
coefficients
from
programmed in the CPW registers.
the
values
2-0
RSV
Reserved.
Must be kept at 0 for normal
operation.
Table 39 - Custom Tx Pulse Enable
(Page 2, Address 11H) (T1)
Bit
Name
Functional Description
7
RSV
Reserved.
Must be kept low for normal
operation.
6-0
CP6-0
Custom Pulse.
These bits provide the
capability
for
magnitude setting for the TTIP/TRING
line driver A/D converter during the first
phase of a mark. The greater the
binary number loaded into the register,
the greater the amplitude driven out.
This feature is enabled when the
control bit 3 - CPL of the Custom Tx
Pulse Enable Register - address 11H
of Page 2 is set high.
programming
the
Table 40 - Custom Pulse Word 1
(Page 2, Address 1CH) (T1)
相關(guān)PDF資料
PDF描述
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
MT9075A E1 Single Chip Transceiver
MT9075AL E1 Single Chip Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9074_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
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MT9074AL1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays
MT9074AP 制造商:Microsemi Corporation 功能描述:
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