參數(shù)資料
型號(hào): MT9074
廠商: Mitel Networks Corporation
英文描述: T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
中文描述: T1/E1/J1收發(fā)單芯片收發(fā)器(T1/E1/J1收發(fā)單片收發(fā)器)
文件頁(yè)數(shù): 44/120頁(yè)
文件大?。?/td> 362K
代理商: MT9074
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MT9074
Advance Information
44
Bit
Name
Functional Description
7
ESFYEL
ESFYellow Alarm
. Setting this bit
while in ESF mode causes a
repeating pattern of eight 1’s
followed by eight 0’s to be insert
onto the transmit FDL (JTS bit set
low - see Data Link Control Word)
or sixteen 1’s (Japan Telecom bit
set high).
6
TXSECY
Transmit Secondary D4 Yellow
Alarm
. Setting this bit (in D4
mode) causes the S bit of
transmit frame 12 to be set.
5
D4YEL
D4 Yellow Alarm
. When set bit 2
of all DS0 channels are forced
low.
4
TxAO
Transmit All Ones.
When low,
this control bit forces a framed or
unframed (depending on the state
of Transmit Alarm Control bit 0)
all ones to be transmit at TTIP
and TRING.
3
LUA
Loop Up Activate
. Setting this bit
forces transmission of a framed
or unframed (depending on the
state of Transmit Alarm Control
bit 0) repeating pattern of 00001.
2
LDA
Loop Down Activate
. Setting
this bit forces transmission of a
framed or unframed (depending
on the state of Transmit Alarm
Control bit 0) repeating pattern of
001.
1
D4SECY
D4 Secondary Alarm
. Set this bit
for
trunks
employing
secondary Yellow Alarm. The Fs
bit in the 12th frame will not be
used for counting errored framing
bits. If a one is received in the Fs
bit position of the 12th frame a
Secondary Yellow Alarm Detect
bit will be set.
the
0
SO
Overhead Sbits Override
. If set,
this bit forces the overhead bits to
be inserted as an overlay on any
of the following alarm conditions:
i) transmit all ones, ii) loop up
code insertion, iii) loop down code
insertion.
Table 22 - Transmit Alarm Control Word (T1)
(Page 1, Address 11H)
Bit
Name
Functional Description
7
EDL
Enable Data Link
. Setting this bit
multiplexes
the
clocked in on pin TxDL into the
FDL bit position (ESF mode) or the
Fs position (D4 mode).
serial
stream
6
BIOMEn
Bit Oriented Messaging Enable
.
Setting
this
transmission of bit - oriented
messages on the ESF facility data
link. The actual message transmit
at any one time is contained in the
BIOMTx register (page 1, address
13H). The receive bit - oriented
message register is always active,
although the interrupt associated
with it may be masked.
bit
enables
5
HDLC0
HDLC0 Enable
. Setting this bit
selects
the
controller for transmission of data
link information in the FDL Sbits of
an ESF frame. The HDLC receiver
is
always
active,
interrupts associated with it may
be masked.
internal
HDLC
although
4
HDLC1
HDLC1 Enable
. Setting this bit
selects
the
controller for transmission on DS1
channel 24. The HDLC receiver is
always active, although interrupts
associated with it may be masked.
internal
HDLC
3
TxSYNC
Transmit
Setting this bit causes the transmit
multiframe
boundary
internally synchronized to the
incoming Sbits on DSTi channel
31 bit 0.
Synchronization
.
to
be
2
TRSP
Transparent Mode
. Setting this
bit causes unframed data to be
transmit from DSTi channels 0 to
23 and channel 31 bit 7 to be
transmit transparently onto the
DS1 line. Unframed data received
from the DS1 line is piped out on
DSTo channels 0 to 23 and
channel 31 bit 0.
Table 23 - Data Link Control Word (T1)
(Page 1, Address 12H)
相關(guān)PDF資料
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參數(shù)描述
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