參數(shù)資料
型號(hào)： MT48LC8M16A2BB-6ALIT:G
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
封裝： 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60
文件頁(yè)數(shù)： 39/57頁(yè)
文件大?。?/td> 1506K
44
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM.pmd – Rev. J; Pub. 1/05
2001 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16
SDRAM
NOTE: 1. For this example, the burst length = 1, the CAS latency = 2, and the READ burst is followed by a “manual”
PRECHARGE.
2. x16: A9 and A11 = “Don’t Care”
x8: A11 = “Don’t Care”
3. PRECHARGE command not allowed or tRAS would be violated.
*CAS latency indicated in parentheses.
-6A
-7E
-75
SYMBOL*
MIN MAX MIN MAX MIN MAX UNITS
tCMH
0.8
ns
tCMS
1.5
ns
tHZ(3)
5.4
ns
tHZ(2)
5.4
6
ns
tLZ
1
ns
tOH
3
ns
tRAS
42
120,000
37
120,000
44
120,000
ns
tRC
60
66
ns
tRCD
18
15
20
ns
tRP
18
15
20
ns
TIMING PARAMETERS
-6A
-7E
-75
SYMBOL*
MIN MAX MIN MAX MIN MAX UNITS
tAC (3)
5.4
ns
tAC (2)
5.4
6
ns
tAH
0.8
ns
tAS
1.5
ns
tCH
2.5
ns
tCL
2.5
ns
tCK (3)
6
7
7.5
ns
tCK (2)
7.5
10
ns
tCKH
0.8
ns
tCKS
1.5
ns
SINGLE READ – WITHOUT AUTO PRECHARGE 1
ALL BANKS
tCH
tCL
tCK
tAC
tLZ
tRP
tRAS
tRCD
CAS Latency
tRC
tOH
DOUT m
tCMH
tCMS
tAH
tAS
tAH
tAS
tAH
tAS
ROW
BANK
BANK(S)
BANK
ROW
BANK
tHZ
tCMH
tCMS
NOP
PRECHARGE
ACTIVE
NOP
READ
ACTIVE
NOP
DISABLE AUTO PRECHARGE
SINGLE BANKS
DON’T CARE
UNDEFINED
COLUMN m2
tCKH
tCKS
T0
T1
T2
T3
T4
T5
T6
T7
T8
DQM /
DQML, DQMH
CKE
CLK
A0-A9, A11
DQ
BA0, BA1
A10
COMMAND
3
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