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| 型號： | MT48LC8M16A2BB-6ALIT:G |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| 封裝： | 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 15/57頁 |
| 文件大?。?/td> | 1506K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM.pmd – Rev. J; Pub. 1/05
2001 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16
SDRAM
WRITEs
WRITE bursts are initiated with a WRITE command,
as shown in Figure 13.
The starting column and bank addresses are pro-
vided with the WRITE command, and auto precharge is
either enabled or disabled for that access. If auto
precharge is enabled, the row being accessed is
precharged at the completion of the burst. For the ge-
neric WRITE commands used in the following illustra-
tions, auto precharge is disabled.
During WRITE bursts, the first valid data-in element
will be registered coincident with the WRITE command.
Subsequent data elements will be registered on each
successive positive clock edge. Upon completion of a
fixed-length burst, assuming no other commands have
been initiated, the DQs will remain High-Z and any addi-
tional input data will be ignored (see Figure 14). A full-
page burst will continue until terminated. (At the end of
the page, it will wrap to column 0 and continue.)
Data for any WRITE burst may be truncated with a
subsequent WRITE command, and data for a fixed-length
WRITE burst may be immediately followed by data for a
WRITE command. The new WRITE command can be
issued on any clock following the previous WRITE com-
mand, and the data provided coincident with the new
command applies to the new command. An example is
shown in Figure 15. Data n + 1 is either the last of a burst
of two or the last desired of a longer burst. The 128Mb
SDRAM uses a pipelined architecture and therefore does
not require the 2n rule associated with a prefetch archi-
tecture. A WRITE command can be initiated on any clock
cycle following a previous WRITE command. Full-speed
random write accesses within a page can be performed to
the same bank, as shown in Figure 16, or each subsequent
WRITE may be performed to a different bank.
Figure 15
WRITE to WRITE
Figure 14
WRITE Burst
CLK
DQ
T2
T1
T0
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL n
BANK,
COL b
DIN
n
DIN
n + 1
DIN
b
NOTE: DQM is LOW. Each WRITE command may
be to any bank.
DON’T CARE
TRANSITIONING DATA
Figure 13
WRITE Command
CS#
WE#
CAS#
RAS#
CKE
CLK
COLUMN
ADDRESS
A10
HIGH
ENABLE AUTO PRECHARGE
DISABLE AUTO PRECHARGE
A0-A9, A11, A12: x4
A0-A9, A11: x8
A0-A9: x16
A12: x8
A11, A12: x16
BA0, BA, 1
BANK
ADDRESS
CLK
DQ
DIN
n
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
DON’T CARE
WRITE
DIN
n + 1
NOP
BANK,
COL n
NOTE: Burst length = 2. DQM is LOW.
TRANSITIONING DATA
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