參數(shù)資料
型號(hào)： MT48LC8M16A2BB-6ALIT:G
元件分類： DRAM
英文描述： 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60
封裝： 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60
文件頁數(shù)： 2/57頁
文件大?。?/td> 1506K
10
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM.pmd – Rev. J; Pub. 1/05
2001 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16
SDRAM
NOTE: 1. For full-page accesses: y = 2,048 (x4), y = 1,024
(x8), y = 512 (x16).
2. For a burst length of two, A1-A9, A11 (x4), A1-A9
(x8) or A1-A8 (x16) select the block-of-two burst;
A0 selects the starting column within the block.
3. For a burst length of four, A2-A9, A11 (x4), A2-A9
(x8) or A2-A8 (x16) select the block-of-four burst;
A0-A1 select the starting column within the block.
4. For a burst length of eight, A3-A9, A11 (x4), A3-
A9 (x8) or A3-A8 (x16) select the block-of-eight
burst; A0-A2 select the starting column within the
block.
5. For a full-page burst, the full row is selected and
A0-A9, A11 (x4), A0-A9 (x8) or A0-A8 (x16) select
the starting column.
6. Whenever a boundary of the block is reached
within a given sequence above, the following
access wraps within the block.
7. For a burst length of one, A0-A9, A11 (x4), A0-A9
(x8) or A0-A8 (x16) select the unique column to be
accessed, and mode register bit M3 is ignored.
Table 1
Burst Definition
Burst
Starting Column
Order of Accesses Within a Burst
Length
Address
Type = Sequential Type = Interleaved
A0
2
0
0-1
1
1-0
A1 A0
0
0-1-2-3
4
0
1
1-2-3-0
1-0-3-2
1
0
2-3-0-1
1
3-0-1-2
3-2-1-0
A2 A1 A0
0
0-1-2-3-4-5-6-7
0
1
1-2-3-4-5-6-7-0
1-0-3-2-5-4-7-6
0
1
0
2-3-4-5-6-7-0-1
2-3-0-1-6-7-4-5
8
0
1
3-4-5-6-7-0-1-2
3-2-1-0-7-6-5-4
1
0
4-5-6-7-0-1-2-3
1
0
1
5-6-7-0-1-2-3-4
5-4-7-6-1-0-3-2
1
0
6-7-0-1-2-3-4-5
6-7-4-5-2-3-0-1
1
7-0-1-2-3-4-5-6
7-6-5-4-3-2-1-0
Full
n = A0-A11/9/8
Cn, Cn + 1, Cn + 2
Page
Cn + 3, Cn + 4...
Not Supported
(y)
(location 0-y)
…Cn - 1,
Cn…
M3 = 0
1
2
4
8
Reserved
Full Page
M3 = 1
1
2
4
8
Reserved
Operating Mode
Standard Operation
All other states reserved
0
-
0
-
Defined
-
0
1
Burst Type
Sequential
Interleaved
CAS Latency
Reserved
2
3
Reserved
Burst Length
M0
0
1
0
1
0
1
0
1
Burst Length
CAS Latency
BT
A9
A7
A6
A5
A4
A3
A8
A2
A1
A0
Mode Register (Mx)
Address Bus
9
7
65
4
3
8
2
1
0
M1
0
1
0
1
M2
0
1
M3
M4
0
1
0
1
0
1
0
1
M5
0
1
0
1
M6
0
1
M6-M0
M8
M7
Op Mode
A10
A11
10
11
Reserved* WB
0
1
Write Burst Mode
Programmed Burst Length
Single Location Access
M9
*Should program
M11, M10 = “0, 0”
to ensure compatibility
with future devices.
Figure 1
Mode Register Definition
Burst Type
Accesses within a given burst may be programmed to
be either sequential or interleaved; this is referred to as
the burst type and is selected via bit M3.
The ordering of accesses within a burst is determined
by the burst length, the burst type and the starting col-
umn address, as shown in Table 1.
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