- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299522 > MT48LC8M16A2BB-6ALIT:G 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 PDF資料下載
參數(shù)資料
| 型號： | MT48LC8M16A2BB-6ALIT:G |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| 封裝： | 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 13/57頁 |
| 文件大小： | 1506K |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁
20
PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM.pmd – Rev. J; Pub. 1/05
2001 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16
SDRAM
A fixed-length READ burst may be followed by, or
truncated with, a PRECHARGE command to the same
bank (provided that auto precharge was not activated),
and a full-page burst may be truncated with a
PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before
the clock edge at which the last desired data element is
valid, where x equals the CAS latency minus one. This is
shown in Figure 11 for each possible CAS latency; data
element n + 3 is either the last of a burst of four or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met. Note that part of the row
precharge time is hidden during the access of the last
data element(s).
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
Figure 11
READ to PRECHARGE
DON’T CARE
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
PRECHARGE
ACTIVE
t RP
T7
NOTE: DQM is LOW.
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
PRECHARGE
ACTIVE
t RP
T7
X = 1 cycle
CAS Latency = 2
CAS Latency = 3
X = 2 cycles
BANK a,
COL n
BANK a,
ROW
BANK
(a or all)
BANK a,
COL n
BANK a,
ROW
BANK
(a or all)
TRANSITIONING DATA
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT49H8M36HU-33 | 8M X 36 DDR DRAM, 0.3 ns, PBGA144 |
| MT4C1024DJ-6L | 1M X 1 FAST PAGE DRAM, 60 ns, PDSO20 |
| MT4C2M8A1DJ-7STR | 2M X 8 FAST PAGE DRAM, 70 ns, PDSO28 |
| MT4LC1M16C5TG-8S | 1M X 16 FAST PAGE DRAM, 80 ns, PDSO44 |
| MT4LC2M8A1DJ-6TR | 2M X 8 FAST PAGE DRAM, 60 ns, PDSO28 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。