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| 型號(hào)： | MT48LC8M16A2BB-6ALIT:G |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| 封裝： | 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 30/57頁 |
| 文件大?。?/td> | 1506K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM.pmd – Rev. J; Pub. 1/05
2001 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16
SDRAM
15. Timing actually specified by tWR plus tRP; clock(s)
specified as a reference only at minimum cycle rate.
16. Timing actually specified by tWR.
17. Required clocks are specified by JEDEC functionality
and are not dependent on any timing parameter.
18. The IDD current will increase or decrease propor-
tionally according to the amount of frequency alter-
ation for the test condition.
19. Address transitions average one transition every two
clocks.
20. CLK must be toggled a minimum of two times during
this period.
21. Based on tCK = 7.5ns for -75/-7E, and tCK = 6ns for
-6A .
22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width
≤ 3ns, and the pulse width cannot be greater than one
third of the cycle rate. VIL undershoot: VIL (MIN) = -2V
for a pulse width
≤ 3ns.
23. The clock frequency must remain constant (stable
clock is defined as a signal cycling within timing
constraints specified for the clock pin) during access
or precharge states (READ, WRITE, including tWR,
and PRECHARGE commands). CKE may be used to
reduce the data rate.
24. Auto precharge mode only. The precharge timing
budget (tRP) begins 6ns for -6A, 7ns for -7E, and
7.5ns for -75 after the first clock delay, after the last
WRITE is executed.
25. Precharge mode only.
26. JEDEC and PC100 specify three clocks.
27. tAC for -75/-7E at CL = 3 with no load is 4.6ns and is
guaranteed by design.
28. Parameter guaranteed by design.
29. PC100 specifies a maximum of 4pF.
30. PC100 specifies a maximum of 5pF.
31. PC100 specifies a maximum of 6.5pF.
32. For -75, CL = 3 and tCK = 7.5ns; for -7E, CL = 2 and
tCK = 7.5ns, and CL = 3 and tCK = 6ns.
33. CKE is HIGH during refresh command period
tRFC (MIN) else CKE is LOW. The IDD6 limit is actu-
ally a nominal value and does not result in a fail
value.
34. PC133 specifies a minimum of 2.5pF.
35. PC133 specifies a minimum of 2.5pF.
36. PC133 specifies a minimum of 3.0pF.
NOTES
1.
All voltages referenced to VSS.
2.
This parameter is sampled. VDD, VDDQ = +3.3V;
f = 1 MHz, TA = 25°C; pin under test biased at 1.4V.
3.
IDD is dependent on output loading and cycle rates.
Specified values are obtained with minimum cycle
time and the outputs open.
4.
Enables on-chip refresh and address counters.
5.
The minimum specifications are used only to
indicate cycle time at which proper operation over
the full temperature range (0°C
≤ T
A ≤ +70°C and -
40°C
≤ T
A ≤ +85°C for IT parts) is ensured.
6.
An initial pause of 100s is required after power-up,
followed by two AUTO REFRESH commands, before
proper device operation is ensured. (VDD and VDDQ
must be powered up simultaneously. VSS and VSSQ
must be at same potential.) The two AUTO REFRESH
command wake-ups should be repeated any time
the tREF refresh requirement is exceeded.
7.
AC characteristics assume tT = 1ns.
8.
In addition to meeting the transition rate specifica-
tion, the clock and CKE must transit between VIH and
VIL (or between VIL and VIH) in a monotonic manner.
9.
Outputs measured at 1.5V with equivalent load:
Q
50pF
10. tHZ defines the time at which the output achieves the
open circuit condition; it is not a reference to VOH or
VOL. The last valid data element will meet tOH before
going High-Z.
11. AC timing and IDD tests have VIL = 0V and VIH = 3V, with
timing referenced to 1.5V crossover point. If the in-
put transition time is longer than 1 ns, then the
timing is referenced at VIL (MAX) and VIH (MIN) and
no longer at the 1.5V crossover point. CLK should
always be 1.5V referenced to crossover. Refer to Mi-
cron Technical Note TN-48-09 for more details.
12. Other input signals are allowed to transition no more
than once every two clocks and are otherwise at valid
VIH or VIL levels.
13. IDD specifications are tested after the device is prop-
erly initialized.
14. Timing actually specified by tCKS; clock(s) specified
as a reference only at minimum cycle rate.
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