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參數(shù)資料
| 型號(hào)： | MT48LC8M16A2BB-6ALIT:G |
| 元件分類： | DRAM |
| 英文描述： | 8M X 16 SYNCHRONOUS DRAM, 5.4 ns, PBGA60 |
| 封裝： | 8 X 16 MM, LEAD FREE, PLASTIC, FBGA-60 |
| 文件頁數(shù)： | 16/57頁 |
| 文件大小： | 1506K |
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PDF: 09005aef8091e66d/Source: 09005aef8091e625
Micron Technology, Inc., reserves the right to change products or specifications without notice.
128MSDRAM.pmd – Rev. J; Pub. 1/05
2001 Micron Technology, Inc. All rights reserved.
128Mb: x4, x8, x16
SDRAM
least one clock plus time, regardless of frequency.
In addition, when truncating a WRITE burst, the DQM
signal must be used to mask input data for the clock edge
prior to, and the clock edge coincident with, the
PRECHARGE command. An example is shown in Figure
18. Data n + 1 is either the last of a burst of two or the last
desired of a longer burst. Following the PRECHARGE
command, a subsequent command to the same bank
cannot be issued until tRP is met.
In the case of a fixed-length burst being executed to
completion, a PRECHARGE command issued at the opti-
mum time (as described above) provides the same op-
eration that would result from the same fixed-length
burst with auto precharge. The disadvantage of the
PRECHARGE command is that it requires that the com-
mand and address buses be available at the appropriate
time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate
fixed-length or full-page bursts.
Data for any WRITE burst may be truncated with a
subsequent READ command, and data for a fixed-length
WRITE burst may be immediately followed by a READ
command. Once the READ command is registered, the
data inputs will be ignored, and WRITEs will not be
executed. An example is shown in Figure 17. Data n + 1 is
either the last of a burst of two or the last desired of a
longer burst.
Data for a fixed-length WRITE burst may be followed
by, or truncated with, a PRECHARGE command to the
same bank (provided that auto precharge was not acti-
vated), and a full-page WRITE burst may be truncated
with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued tWR after the
clock edge at which the last desired input data element is
registered. The auto precharge mode requires a tWR of at
Figure 18
WRITE To PRECHARGE
DON’T CARE
DQM
CLK
DQ
T2
T1
T4
T3
T0
COMMAND
ADDRESS
BANK a,
COL n
T5
NOP
WRITE
PRECHARGE
NOP
DIN
n
DIN
n + 1
ACTIVE
t RP
BANK
(a or all)
t WR
BANK a,
ROW
DQM
DQ
COMMAND
ADDRESS
BANK a,
COL n
NOP
WRITE
PRECHARGE
NOP
DIN
n
DIN
n + 1
ACTIVE
t RP
BANK
(a or all)
t WR
NOTE: DQM could remain LOW in this example if the WRITE burst is a fixed length of two.
BANK a,
ROW
T6
NOP
tWR @ tCLK
≥ 15ns
tWR = tCLK < 15ns
TRANSITIONING DATA
Figure 17
WRITE To READ
DON’T CARE
CLK
DQ
T2
T1
T3
T0
COMMAND
ADDRESS
NOP
WRITE
BANK,
COL n
DIN
n
DIN
n + 1
DOUT
b
READ
NOP
BANK,
COL b
NOP
DOUT
b + 1
T4
T5
TRANSITIONING DATA
Figure 16
Random WRITE Cycles
DON’T CARE
CLK
DQ
DIN
n
T2
T1
T3
T0
COMMAND
ADDRESS
WRITE
BANK,
COL n
DIN
a
DIN
x
DIN
m
WRITE
BANK,
COL a
BANK,
COL x
BANK,
COL m
TRANSITIONING DATA
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