參數(shù)資料
型號： MT48LC4M16A2P-75:G
元件分類： DRAM
英文描述： 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54
文件頁數(shù)： 28/72頁
文件大?。?/td> 3455K
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
34
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
Power-Down
Power-down occurs if CKE is registered LOW coincident with a NOP or COMMAND
INHIBIT when no accesses are in progress. If power-down occurs when all banks are
idle, this mode is referred to as precharge power-down; if power-down occurs when
there is a row active in any bank, this mode is referred to as active power-down. Entering
power-down deactivates the input and output buffers, excluding CKE, for maximum
power savings while in standby. The device may not remain in the power-down state
longer than the refresh period (tREF or tREFAT) since no refresh operations are
performed in this mode.
The power-down state is exited by registering a NOP or COMMAND INHIBIT and CKE
HIGH at the desired clock edge (meeting tCKS). See Figure 26 on page 35.
Figure 24:
Terminating a WRITE Burst
Note:
DQMs are LOW.
Figure 25:
PRECHARGE Command
DON’T CARE
CLK
DQ
T2
T1
T0
COMMAND
ADDRESS
BANK,
COL n
WRITE
BURST
TERMINATE
NEXT
COMMAND
DIN
n
(ADDRESS)
(DATA)
TRANSITIONING DATA
CS#
WE#
CAS#
RAS#
CKE
CLK
A10
DON’T CARE
HIGH
All Banks
Bank Selected
A0–A9
BA0,1
BANK
ADDRESS
VALID ADDRESS
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48LC4M16A2P75ITG 制造商:Micron Technology Inc 功能描述:
MT48LC4M16A2P-75ITG 制造商: 功能描述:
MT48LC4M16A2P-7E 制造商:Micron Technology Inc 功能描述:SDRAM 64MBIT 133MHZ 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP, Memory Type:DRAM - Synchronous, Memory Configurat
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