參數(shù)資料
型號(hào)： MT48LC4M16A2P-75:G
元件分類： DRAM
英文描述： 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54
封裝： 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54
文件頁(yè)數(shù)： 21/72頁(yè)
文件大?。?/td> 3455K
PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_2.fm - Rev. N 12/08 EN
28
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
Commands
A fixed-length READ burst may be followed by, or truncated with, a PRECHARGE
command to the same bank (provided that auto precharge was not activated), and a full-
page burst may be truncated with a PRECHARGE command to the same bank. The
PRECHARGE command should be issued x cycles before the clock edge at which the last
desired data element is valid, where x = CL -1. This is shown in Figure 16 for each
possible CL; data element n + 3 is either the last of a burst of four or the last desired of a
longer burst. Following the PRECHARGE command, a subsequent command to the
same bank cannot be issued until tRP is met. Note that part of the row precharge time is
hidden during the access of the last data element(s).
In the case of a fixed-length burst being executed to completion, a PRECHARGE
command issued at the optimum time (as described above) provides the same operation
that would result from the same fixed-length burst with auto precharge. The disadvan-
tage of the PRECHARGE command is that it requires that the command and address
buses be available at the appropriate time to issue the command; the advantage of the
PRECHARGE command is that it can be used to truncate fixed-length or full-page bursts.
Full-page READ bursts can be truncated with the BURST TERMINATE command, and
fixed-length READ bursts may be truncated with a BURST TERMINATE command,
provided that auto precharge was not activated. The BURST TERMINATE command
should be issued x cycles before the clock edge at which the last desired data element is
valid, where x = CL = -1. This is shown in Figure 17 on page 29 for each possible CL; data
element n + 3 is the last desired data element of a longer burst.
Figure 16:
READ-to-PRECHARGE
Note:
DQM is LOW.
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
PRECHARGE
NOP
T7
DON’T CARE
CLK
DQ
DOUT
n
T2
T1
T4
T3
T6
T5
T0
COMMAND
ADDRESS
READ
NOP
BANK,
COL n
NOP
DOUT
n + 1
DOUT
n + 2
DOUT
n + 3
PRECHARGE
NOP
X = 1 cycle
CL = 2
CL = 3
X = 2 cycles
TRANSITIONING DATA
相關(guān)PDF資料
PDF描述
M93C06-MB6G 16 X 16 MICROWIRE BUS SERIAL EEPROM, DSO8
MT48LC4M16A2F4-6IT:G 4M X 16 SYNCHRONOUS DRAM, 5.5 ns, PBGA54
MT46V32M8FG-6TIT:G 32M X 8 DDR DRAM, 0.7 ns, PBGA60
MT46V32M8BG-6AT:G 32M X 8 DDR DRAM, 0.7 ns, PBGA60
M29F800FB55N3E2 512K X 16 FLASH 5V PROM, 55 ns, PDSO48
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT48LC4M16A2P75ITG 制造商:Micron Technology Inc 功能描述:
MT48LC4M16A2P-75ITG 制造商: 功能描述:
MT48LC4M16A2P-7E 制造商:Micron Technology Inc 功能描述:SDRAM 64MBIT 133MHZ 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP, Memory Type:DRAM - Synchronous, Memory Configurat
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*