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參數(shù)資料
| 型號： | MT48LC4M16A2P-75:G |
| 元件分類： | DRAM |
| 英文描述： | 4M X 16 SYNCHRONOUS DRAM, 5.4 ns, PDSO54 |
| 封裝： | 0.400 INCH, ROHS COMPLIANT, PLASTIC, TSOP2-54 |
| 文件頁數(shù)： | 12/72頁 |
| 文件大?。?/td> | 3455K |
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PDF: 09005aef80725c0b/Source: 09005aef806fc13c
Micron Technology, Inc., reserves the right to change products or specifications without notice.
64MSDRAM_1.fm - Rev. N 12/08 EN
2
2000 Micron Technology, Inc. All rights reserved.
64Mb: x4, x8, x16 SDRAM
General Description
General Description
The Micron 64Mb SDRAM is a high-speed CMOS, dynamic random-access memory
containing 67,108,864 bits. It is internally configured as a quad-bank DRAM with a
synchronous interface (all signals are registered on the positive edge of the clock signal,
CLK). Each of the x4’s 16,777,216-bit banks is organized as 4,096 rows by 1,024 columns
by 4 bits. Each of the x8’s 16,777,216-bit banks is organized as 4,096 rows by 512 columns
by 8 bits. Each of the x16’s 16,777,216-bit banks is organized as 4,096 rows by 256
columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; accesses start at a selected
location and continue for a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits registered coincident with the
ACTIVE command are used to select the bank and row to be accessed (BA0, BA1 select
the bank; A0–A11 select the row). The address bits registered coincident with the READ
or WRITE command are used to select the starting column location for the burst access.
The SDRAM provides for programmable read or write burst lengths of 1, 2, 4, or 8 loca-
tions, or the full page, with a burst terminate option. An auto precharge function may be
enabled to provide a self-timed row precharge that is initiated at the end of the burst
sequence.
The 64Mb SDRAM uses an internal pipelined architecture to achieve high-speed opera-
tion. This architecture is compatible with the 2n rule of prefetch architectures, but it also
allows the column address to be changed on every clock cycle to achieve a high-speed,
Table 2:
Key Timing Parameters
CL = CAS (READ) latency
Speed Grade
Clock Frequency
Access Time
Setup Time
Hold Time
CL = 2
CL = 3
-6
166 MHz
–
5.5ns
1.5ns
1ns
-7E
143 MHz
–
5.4ns
1.5ns
0.8ns
-75
133 MHz
–
5.4ns
1.5ns
0.8ns
-7E
133 MHz
5.4ns
–
1.5ns
0.8ns
-75
100 MHz
6ns
–
1.5ns
0.8ns
Table 3:
64Mb SDRAM Part Numbers
Part Numbers
Architecture
Package
MT48LC16M4A2TG
16 Meg x 4
54-pin TSOP II
MT48LC16M4A2P
16 Meg x 4
54-pin TSOP II
MT48LC8M8A2TG
8 Meg x 8
54-pin TSOP II
MT48LC8M8A2P
8 Meg x 8
54-pin TSOP II
MT48LC4M16A2TG
4 Meg x 16
54-pin TSOP II
MT48LC4M16A2P
4 Meg x 16
54-pin TSOP II
MT48LC4M16A2B41
4 Meg x 16
54-ball VFBGA
MT48LC4M16A2F41
4 Meg x 16
54-ball VFBGA
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT48LC4M16A2P75ITG | 制造商:Micron Technology Inc 功能描述: |
| MT48LC4M16A2P-75ITG | 制造商: 功能描述: |
| MT48LC4M16A2P-7E | 制造商:Micron Technology Inc 功能描述:SDRAM 64MBIT 133MHZ 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP 制造商:Micron Technology Inc 功能描述:SDRAM, 64MBIT, 133MHZ, 54TSOP, Memory Type:DRAM - Synchronous, Memory Configurat |
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