參數(shù)資料
型號： MT28F640J3
廠商： Micron Technology, Inc.
英文描述： 64Mb Flash Memory(64Mb閃速存儲器)
中文描述： 64MB Flash記憶體（64兆閃速存儲器）
文件頁數(shù)： 5/45頁
文件大?。?/td> 317K
代理商： MT28F640J3
5
64Mb, 32Mb SirusFlash Memory
MT28F640J3_2.p65 – Rev. 1, Pub. 12/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb, 32Mb
SIRUSFLASH MEMORY
PRELIMINARY
Figure 1
Memory Map
Table 1
Chip Enable Truth Table
CE2
V
IL
V
IL
V
IL
V
IL
V
IH
V
IH
V
IH
V
IH
CE1
V
IL
V
IL
V
IH
V
IH
V
IL
V
IL
V
IH
V
IH
CE0
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
DEVICE
Enabled
Disabled
Disabled
Disabled
Enabled
Enabled
Enabled
Disabled
NOTE:
For single-chip applications, CE2 and CE1 can be
connected to GND.
128KB Block 31
128KB Block 1
128KB Block 0
64K-Word Block
63
64K-Word Block
31
64K-Word Block
1
64K-Word Block
0
7FFFFFh
7E0000h
3FFFFFh
3E0000h
03FFFFh
020000h
01FFFFh
000000h
3FFFFFh
3F0000h
1FFFFFh
1F0000h
01FFFFh
010000h
00FFFFh
000000h
3
6
Byte-Wide (x8) Mode
Word-Wide (x16) Mode
A0–A22: 64Mb
A0–A21: 32Mb
A1–A22: 64Mb
A1–A21: 32Mb
128KB Block
63
MEMORY ARCHITECTURE
The MT28F640J3 and MT28F320J3 memory array
architecture is divided into sixty-four or thirty-two
128KB blocks, respectively (see Figure 1). The internal
architecture allows greater flexibility when updating
data because individual code portions can be updated
independently of the rest of the code.
OUTPUT DISABLE
The device outputs are disabled with OE# at a logic
HIGH level (V
IH
). Output pins DQ0–DQ15 are placed in
High-Z.
STANDBY
CE0, CE1, and CE2 can disable the device (see
Table 1) and place it in standby mode, which substan-
tially reduces device power consumption. DQ0–DQ15
outputs are placed in High-Z, independent of OE#. If
deselected during block erase, program, or lock bit con-
figuration, the ISM continues functioning and consum-
ing active power until the operation completes.
RESET/POWER-DOWN
RP# puts the device into the reset/power-down
mode when set to V
IL
.
During read, RP# LOW deselects the memory, places
output drivers in High-Z, and turns off internal cir-
cuitry. RP# must be held LOW for a minimum of
t
PLPH.
t
RWH is required after return from reset mode until
initial memory access outputs are valid. After this wake-
up interval, normal operation is restored. The com-
mand execution logic (CEL) is reset to the read array
mode and the status register is set to 80h.
During block erase, program, or lock bit configura-
tion, RP# LOW aborts the operation. In default mode,
STS transitions LOW and remains LOW for a maximum
time of
t
PLPH +
t
PHRH, until the RESET operation is
complete. Any memory content changes are no longer
valid; the data may be partially corrupted after a pro-
gram or partially changed after an erase or lock bit
configuration. After RP# goes to logic HIGH (V
IH
), and
after
t
RS, another command can be written.
BUS OPERATION
All bus cycles to and from the Flash memory must
conform to the standard microprocessor bus cycles.
The local CPU reads and writes Flash memory in-
system.
READ
Information can be read from any block, query, iden-
tifier codes, or status register, regardless of the V
PEN
voltage. The device automatically resets to read array
mode upon initial device power-up or after exit from
reset/power-down mode. To access other read mode
commands (READ ARRAY, READ QUERY, READ IDEN-
TIFIER CODES, or READ STATUS REGISTER), these
commands should be issued to the CUI. Six control
pins dictate the data flow in and out of the device: CE0,
CE1, CE2, OE#, WE#, and RP#. In system designs using
multiple SirusFlash devices, CE0, CE1, and CE2 (CEx)
select the memory device (see Table 1). To drive data
out of the device and onto the I/O bus, OE# must be
active and WE# must be inactive (V
IH
).
When reading information in read array mode, the
device defaults to asynchronous page mode, thus pro-
viding a high data transfer rate for memory subsystems.
In this state, data is internally read and stored in a
high-speed page buffer. A0–A2 select data in the page
buffer. Asynchronous page mode, with a page size of
four words or eight bytes, is supported with no addi-
tional commands required.
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參數(shù)描述
MT28F640J3BS-115 ET 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
MT28F640J3BS-115 ET TR 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤
MT28F640J3BS-115 GMET 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
MT28F640J3BS-115 GMET TR 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲器:閃存 存儲器類型:FLASH 存儲容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤
MT28F640J3BS-115 MET 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲器:RAM 存儲器類型:SDRAM 存儲容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
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