參數(shù)資料
型號(hào)： MT28F640J3
廠商： Micron Technology, Inc.
英文描述： 64Mb Flash Memory(64Mb閃速存儲(chǔ)器)
中文描述： 64MB Flash記憶體（64兆閃速存儲(chǔ)器）
文件頁數(shù)： 22/45頁
文件大小： 317K
代理商： MT28F640J3
22
64Mb, 32Mb SirusFlash Memory
MT28F640J3_2.p65 – Rev. 1, Pub. 12/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb, 32Mb
SIRUSFLASH MEMORY
PRELIMINARY
Table 17
Configuration Coding Definitions
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses LOW with a typical pulse width of 250ns.
RESERVED
BITS 7–2
DQ7–DQ2 = Reserved
DQ1–DQ0 = STS Pin Configuration Codes
00 = Default, RY/BY# level mode
(device ready) indication
01 = Pulse on Erase Complete
10 = Pulse on Program Complete
11 = Pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse
modes such that the STS pin pulses LOW then HIGH
when the operation indicated by the given
configuration is completed.
Configuration command sequences for STS pin
configuration (masking bits DQ7–DQ2 to 00h) are as
follows:
Default RY/BY# level mode: B8h, 00h
ER INT (Erase Interrupt): B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt): B8h, 02h
Pulse-on-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
PULSE ON
PROGRA M
COMPLETE
1
BIT 1
DQ7–DQ2 are reserved for future use.
PULSE ON
ERA SE
COMPLETE
1
BIT 0
Default RY/BY# level mode (DQ1–DQ0 = 00)
Used to control HOLD to a memory controller to
prevent accessing a Flash memory subsystem
while any Flash device’s ISM is busy.
Configuration 01 ER INT, pulse mode
Used to generate a system interrupt pulse when
any Flash device in an array has completed a
BLOCK ERASE or sequence of queued BLOCK
ERASEs; helpful for reformatting blocks after file
system free space reclamation or “cleanup.”
Configuration 10 PR INT, pulse mode
Used to generate a system interrupt pulse when
any Flash device in an array has completed a
PROGRAM operation. Provides highest perfor-
mance for enabling continuous BUFFER WRITE
operations.
Configuration 11 ER/PR INT, pulse mode
Used to generate system interrupts to trigger
enabling of Flash arrays when either ERASE or
PROGRAM operations are completed and a
common interrupt service routine is desired.
SET BLOCK LOCK BITS COMMAND
A flexible block locking and unlocking scheme is
enabled via a combination of block lock bits. The block
lock bits gate PROGRAM and ERASE operations. Using
the SET BLOCK LOCK BITS command, individual block
lock bits can be set. This command is invalid when the
ISM is running or when the device is suspended. SET
BLOCK LOCK BITS commands are executed by a two-
cycle sequence. The set block lock bits setup, along
with appropriate block address, is followed by the set
block lock bits confirm and an address within the block
to be locked. The ISM then controls the set lock bit
algorithm. When the sequence is written, the device
automatically outputs status register data when read
(see Figure 9). The CPU can detect the completion of
the set block lock bit event by analyzing the STS pin
output or status register bit SR7. Upon completion of
set block lock bits operation, status register bit SR4
should be checked for error. If an error is detected, the
status register should be cleared. The CEL remains in
read status register mode until a new command is is-
sued. This two-step sequence of setup followed by ex-
ecution ensures that lock bits are not accidentally set.
An invalid SET BLOCK LOCK BITS command results in
status register bits SR4 and SR5 being set to “1.” Also,
reliable operation occurs only when V
CC
and V
PEN
are
valid. When V
PEN
≤
V
PENLK
, lock bit contents are protected
against any data change.
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MT28F640J3BS-115 ET 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
MT28F640J3BS-115 ET TR 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤
MT28F640J3BS-115 GMET 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
MT28F640J3BS-115 GMET TR 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:378 系列:- 格式 - 存儲(chǔ)器:閃存 存儲(chǔ)器類型:FLASH 存儲(chǔ)容量:8M（1M x 8，512K x 16） 速度:110ns 接口:并聯(lián) 電源電壓:2.7 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:48-CBGA 供應(yīng)商設(shè)備封裝:48-CBGA（7x7） 包裝:托盤
MT28F640J3BS-115 MET 功能描述:IC FLASH 64MBIT 115NS 64FBGA RoHS:是 類別:集成電路 (IC) >> 存儲(chǔ)器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:- 格式 - 存儲(chǔ)器:RAM 存儲(chǔ)器類型:SDRAM 存儲(chǔ)容量:256M（8Mx32） 速度:143MHz 接口:并聯(lián) 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:90-VFBGA 供應(yīng)商設(shè)備封裝:90-VFBGA（8x13） 包裝:托盤 其它名稱:Q2841869
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