參數(shù)資料
型號(hào): MT28F640J3
廠商: Micron Technology, Inc.
英文描述: 64Mb Flash Memory(64Mb閃速存儲(chǔ)器)
中文描述: 64MB Flash記憶體(64兆閃速存儲(chǔ)器)
文件頁(yè)數(shù): 4/45頁(yè)
文件大?。?/td> 317K
代理商: MT28F640J3
4
64Mb, 32Mb SirusFlash Memory
MT28F640J3_2.p65 – Rev. 1, Pub. 12/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
64Mb, 32Mb
SIRUSFLASH MEMORY
PRELIMINARY
PIN DESCRIPTIONS
56-PIN TSOP
NUMBERS
55
SY MBOL
WE#
TY PE
Input
DESCRIPTION
Write Enable: Determines if a given cycle is a WRITE cycle. If WE#
is LOW, the cycle is either a WRITE to the command execution
logic (CEL) or to the memory array. Addresses and data are
latched on the rising edge of the WE# pulse.
Chip Enable: Three CE pins enable the use of multiple Flash
devices in the system without requiring additional logic. The
device can be configured to use a single CE signal by tying CE1
and CE2 to ground and then using CE0 as CE. Device selection
occurs with the first edge of CE0, CE1, or CE2 (CEx) that enables
the device. Device deselection occurs with the first edge of CEx
that disables the device (see Table 1).
Reset/Power-Down: When LOW, RP# clears the status register, sets
the ISM to the array read mode, and places the device in deep
power-down mode. All inputs, including CEx, are “Don’t Care,”
and all outputs are High-Z. RP# must be held at V
IH
during all
other modes of operation.
Output Enables: Enables data ouput buffers when LOW. When
OE# is HIGH, the output buffers are disabled.
Address inputs during READ and WRITE operations. A0 is only
used in x8 mode. A22 (pin 1) is only available on the 64Mb
device.
14, 2, 29
CE0, CE1,
CE2
Input
16
RP#
Input
54
OE#
Input
32, 28, 27, 26, 25, 24,
23, 22, 20, 19, 18, 17,
13, 12, 11, 10, 8, 7,
6, 5, 4, 3, 1
31
A0–A21/
(A22)
Input
BYTE#
Input
BYTE# LOW places the device in the x8 mode. BYTE# HIGH places
the device in the x16 mode and turns off the A0 input buffer.
Address A1 becomes the lowest order address in x16 mode.
Necessary voltage for erasing blocks, programming data, or
configuring lock bits. Typically, V
PEN
is connected to V
CC
. When
V
PEN
V
PENLK
, this pin enables hardware write protect.
Data I/O: Data output pins during any READ operation or data
input pins during a WRITE. DQ8–DQ15 are not used in byte
mode.
Status: Indicates the status of the ISM. When configured in level
mode, default mode it acts as an RY/BY# pin. When configured in
its pulse mode, it can pulse to indicate program and/or erase
completion. Tie STS to V
CC
Q through a pull-up resistor.
V
CC
Q controls the output voltages. To obtain output voltage
compatible with system data bus voltages, connect V
CC
Q to the
system supply voltage.
Power Supply: 2.7V to 3.6V.
Ground.
No Connect: These pins may be driven or left unconnected. (Pin 1
is a NC on the 32Mb device.)
15
V
PEN
Input
33, 35, 38, 40, 44, 46, DQ0–DQ15
49, 51, 34, 36, 39, 41,
45, 47, 50, 52
53
Input/
Output
STS
Output
43
V
CC
Q
Supply
9, 37
V
CC
V
SS
NC
Supply
Supply
21, 42, 48
30, 56
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