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參數(shù)資料
| 型號： | MT28F016S5VG-9 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY |
| 中文描述： | 2邁可× 8的SMART 5偶扇區(qū)快閃記憶體 |
| 文件頁數(shù)： | 8/24頁 |
| 文件大?。?/td> | 282K |
| 代理商： | MT28F016S5VG-9 |
8
2 Meg x 8 Smart 5 Even-Sectored Flash Memory
F42.p65 – Rev. 1/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
Table 1
Command Set
COMMAND
RESERVED
HEX CODE
00H
DESCRIPTION
This command and all unlisted commands are invalid and
should not be called. These commands are reserved to allow
for future feature enhancements.
Must be issued after any other command cycle before the
array can be read. It is not necessary to issue this command
after power-up or RESET.
Allows the device ID and manufacturer ID to be read. Please
refer to Table 3 for more information on the various device
configuration registers.
Allows the status register to be read. Please refer to Table 2
for more information on the status register bits.
Clears status register bits 3-5, which cannot be cleared by the
ISM.
The first command given in the two-cycle ERASE sequence.
The ERASE will not be completed unless followed by ERASE
CONFIRM.
The second command given in the two-cycle ERASE se-
quence. Must follow an ERASE SETUP to be valid. Also used
during a WRITE/ERASE SUSPEND to resume the WRITE or
ERASE.
The first command given in the two-cycle WRITE sequence.
The write data and address are given in the following cycle
to complete the WRITE.
Requests a halt of the ERASE and puts the device into the
erase suspend mode. When the device is in this mode, only
READ STATUS REGISTER, READ ARRAY and ERASE CONFIRM
(ERASE RESUME) commands may be executed.
READ ARRAY
FFH
READ DEVICE CONFIGURATION
90H
READ STATUS REGISTER
70H
CLEAR STATUS REGISTER
50H
ERASE SETUP
20H
ERASE CONFIRM
D0H
WRITE SETUP
40H or
10H
ERASE SUSPEND
B0H
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