參數(shù)資料
型號(hào)： MT28F016S5VG-9
廠商： Micron Technology, Inc.
英文描述： 2 MEG x 8 SMART 5 EVEN-SECTORED FLASH MEMORY
中文描述： 2邁可× 8的SMART 5偶扇區(qū)快閃記憶體
文件頁(yè)數(shù)： 10/24頁(yè)
文件大?。?/td> 282K
代理商： MT28F016S5VG-9
10
2 Meg x 8 Smart 5 Even-Sectored Flash Memory
F42.p65 – Rev. 1/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
ADVANCE
2 MEG x 8
SMART 5 EVEN-SECTORED FLASH MEMORY
Table 4
Command Sequences
BUS
CYCLES
REQ’D OPERATION ADDRESS DATA OPERATION ADDRESS DATA
1
WRITE
X
FFH
2
WRITE
X
90H
2
WRITE
X
70H
1
WRITE
X
50H
2
WRITE
X
20H
2
WRITE
X
B0H
2
WRITE
X
40H
2
WRITE
X
10H
1ST
CYCLE
2ND
CYCLE
COMMANDS
READ ARRAY
READ DEVICE CONFIGURATION
READ STATUS REGISTER
CLEAR STATUS REGISTER
ERASE SETUP/CONFIRM
ERASE SUSPEND/RESUME
WRITE SETUP/WRITE
ALTERNATE WRITE
NOTES
1
2, 3
4
READ
READ
CA
X
CD
SRD
WRITE
WRITE
WRITE
WRITE
BA
X
WA
WA
D0H
D0H
WD
WD
5, 6
6, 7
6, 7
COMMAND EXECUTION
Commands are issued to bring the device into
different operational modes. Each mode allows specific
operations to be performed. Several modes require a
sequence of commands to be written before they are
reached. The following section describes the properties
of each mode, and Table 4 lists all command sequences
required to perform the desired operation.
READ ARRAY
The array read mode is the initial state of the device
upon power-up and is also entered after a RESET. If the
device is in any other mode, READ ARRAY (FFH) must
be given to return to the array read mode. Unlike the
WRITE SETUP command (40H), READ ARRAY does not
need to be given before each individual read access.
DEVICE CONFIGURATION
To read the device ID and manufacturer compatibil-
ity ID, the READ DEVICE CONFIGURATION (90H)
command must be issued. While the device is in this
mode, specific addresses must be issued to read the
desired information. The manufacturer compatibility
ID is read at 000000H, and the device ID is read at
000001H.
WRITE SEQUENCE
Two consecutive cycles are needed to input data to
the array. WRITE SETUP (40H or 10H) is given in the
first cycle. The next cycle is the WRITE, during which
the write address and data are issued and V
PP
is brought
to V
PPH
. The ISM will now begin to write the byte. V
PP
must be held at V
PPH
until the WRITE is completed (SR7
= 1 and RY/BY# = V
OH
).
While the ISM executes the WRITE, the ISM status
bit (SR7) will be at “0” and RY/BY# = V
OL
, and the device
will not respond to any commands. Any READ opera-
tion will produce the status register contents on DQ0-
DQ7. When the ISM status bit (SR7) is set to a logic 1 and
RY/BY# = V
OH
, the WRITE has been completed, and the
device will go into the status register read mode until
another command is given.
NOTE:
1. Must follow WRITE or ERASE CONFIRM commands to the CEL in order to enable flash array READ cycles.
2. CA = Configuration Address: 00000H for manufacturer compatibility ID and 00001H for device ID.
3. CD = Configuration Data.
4. SRD = Status Register Data.
5. BA = Block Address.
6. Addresses are “Don’t Care” in first cycle but must be held stable.
7. WA = Address to be written; WD = Data to be written to WA.
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