參數(shù)資料
型號(hào)： MT18VDVF6472DG-265XX
元件分類(lèi)： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝： DIMM-184
文件頁(yè)數(shù)： 6/38頁(yè)
文件大?。?/td> 713K
代理商： MT18VDVF6472DG-265XX
PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
14
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Extended Mode Register
Figure 5:
CAS Latency Diagram
Operating Mode
The normal operating mode is selected by issuing a MODE REGISTER SET command
with bits A7–A12 each set to zero, and bits A0–A6 set to the desired values. A DLL reset is
initiated by issuing a MODE REGISTER SET command with bits A7 and A9–A12 each set
to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required
by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER
command is issued to reset the DLL, it should always be followed by a LOAD MODE
REGISTER command to select normal operating mode.
All other combinations of values for A7–A12 are reserved for future use and/or test
modes. Test modes and reserved states should not be used because unknown operation
or incompatibility with future versions may result.
Extended Mode Register
The extended mode register controls functions beyond those controlled by the mode
register; these additional functions are DLL enable/disable and output drive strength.
These functions are controlled via the bits shown in Figure 6, "Extended Mode Register
Definition Diagram," on page 15. The extended mode register is programmed via the
LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and
will retain the stored information until it is programmed again or the device loses power.
The enabling of the DLL should always be followed by a LOAD MODE REGISTER com-
mand to the mode register (BA0/BA1 both LOW) to reset the DLL.
The extended mode register must be loaded when all device banks are idle and no bursts
are in progress, and the controller must wait the specified time before initiating any sub-
sequent operation. Violating either of these requirements could result in unspecified
operation.
CK
CK#
COMMAND
DQ
DQS
CL = 2
READ
NOP
READ
NOP
Burst Length = 4 in the cases shown
Shown with nominal tAC, tDQSCK, and tDQSQ
CK
CK#
COMMAND
DQ
DQS
CL = 2.5
T0
T1
T2
T2n
T3
T3n
T0
T1
T2
T2n
T3
T3n
DON’T CARE
TRANSITIONING DATA
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