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參數(shù)資料
| 型號： | MT18VDVF6472DG-265XX |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 26/38頁 |
| 文件大?。?/td> | 713K |
| 代理商： | MT18VDVF6472DG-265XX |
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PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
32
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Serial Presence-Detect
SPD Clock And Data Conventions
Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (Figure 12, "Data Valid-
SPD Start Condition
All commands are preceded by the start condition, which is a HIGH-to-LOW transition
of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL
lines for the start condition and will not respond to any command until this condition
has been met.
SPD Stop Condition
All communications are terminated by a stop condition, which is a LOW-to-HIGH tran-
sition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device
into standby power mode.
SPD Acknowledge
Acknowledge is a software convention used to indicate successful data transfers. The
transmitting device, either master or slave, will release the bus after transmitting eight
bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge
that it received the eight bits of data (Figure 14, "Acknowledge Response From Receiver,"
The SPD device will always respond with an acknowledge after recognition of a start
condition and its slave address. If both the device and a WRITE operation have been
selected, the SPD device will respond with an acknowledge after the receipt of each sub-
sequent eight-bit word. In the read mode the SPD device will transmit eight bits of data,
release the SDA line and monitor the line for an acknowledge. If an acknowledge is
detected and no stop condition is generated by the master, the slave will continue to
transmit data. If an acknowledge is not detected, the slave will terminate further data
transmissions and await the stop condition to return to standby power mode.
Figure 12:
Data Validity
SCL
SDA
DATA STABLE
DATA
CHANGE
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT-19 | 功能描述:TERM BARRIER 19CIRC DUAL ROW RoHS:是 類別:連接器，互連式 >> 接線座 - 隔板塊 系列:M 標準包裝:10 系列:Beau™ 38780 端接塊類型:阻隔塊 電路數(shù):15 導線入口數(shù)目:30 間距:0.438"（11.12mm） 行數(shù):2 電流:15A 電壓:300V 線規(guī):14-22 AWG 頂部端子:螺釘 底部端子:焊片 阻擋層類型:雙壁（雙） 特點:法蘭 顏色:黑 包裝:散裝 安裝類型:通孔 工作溫度:- 材料 - 絕緣體:聚對苯二甲酸丁二酯（PBT），玻璃纖維增強型 材料可燃性額定值:UL94 V-0 其它名稱:038780-111538780-1115387801115 |
| MT190A | 制造商:Black Box Corporation 功能描述:SMART 64K CSU/DSU |
| MT190AD130 | 制造商:BLACK BOX 功能描述:64K CSU/DSU |
| MT190A-D48 | 制造商:Black Box Corporation 功能描述:Smart 64K CSU/DSUs, 24 48-VDC |
| MT190A-D48-W1 | 制造商:Black Box Corporation 功能描述:1 YEAR WARRANTY FOR MT190A-D48 |
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