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參數(shù)資料
| 型號： | MT18VDVF6472DG-265XX |
| 元件分類： | DRAM |
| 英文描述： | 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184 |
| 封裝： | DIMM-184 |
| 文件頁數(shù)： | 24/38頁 |
| 文件大?。?/td> | 713K |
| 代理商： | MT18VDVF6472DG-265XX |
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PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
30
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Register and PLL Specifications
Notes: 1. The timing and switching specifications for the PLL listed above are critical for proper
operation of DDR SDRAM registered DIMMs. These are meant to be a subset of the param-
eters for the specific device used on the module. Detailed information for this PLL is avail-
able in JEDEC Standard JESD82.
2. The PLL must be able to handle spread spectrum induced skew.
3. Operating clock frequency indicates a range over which the PLL must be able to lock, but
in which it is not required to meet the other timing parameters. (Used for low-speed sys-
tem debug.)
4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of
its feedback signal to its reference signal after power up.
5. Static Phase Offset does not include Jitter.
6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be
met independently of each other.
7. The Output Slew Rate is determined from the IBIS model:
Table 16:
PLL Clock Driver Timing Requirements and Switching Characteristics
Note: 1
Parameter
Symbol
0°C
≤ T
A ≤ +70°C
VDD = 2.5V ± 0.2V
Units
Notes
Min
Nominal
Max
Operating Clock Frequency
fCK
60
-
170
MHz
Input Duty Cycle
tDC
40
-
60
%
Stabilization Time
tSTAB
-
100
ms
Cycle to Cycle Jitter
tJIT
CC
-75
-
75
ps
Static Phase Offset
t
-50
0
50
ps
Output Clock Skew
tSK
O
--
100
ps
Period Jitter
tJIT
PER
-75
-
75
ps
Half-Period Jitter
tJIT
HPER
-100
-
100
ps
Input Clock Slew Rate
tLS
I
1.0
-
4
V/ns
Output Clock Slew Rate
tLS
O
1.0
-
2
V/ns
V
DD/2
GND
V
DD
CDCV857
R=60
Ω
R=60
Ω
V
CK
V
CK
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