參數(shù)資料
型號(hào)： MT18VDVF6472DG-265XX
元件分類(lèi)： DRAM
英文描述： 64M X 72 DDR DRAM MODULE, 0.75 ns, DMA184
封裝： DIMM-184
文件頁(yè)數(shù)： 16/38頁(yè)
文件大小： 713K
代理商： MT18VDVF6472DG-265XX
PDF: 09005aef81c73825/Source: 09005aef81c73837
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DVF18C64_128x72D_2.fm - Rev. A 8/05 EN
23
2003, 2004, 2005 Micron Technology, Inc. All rights reserved.
512MB, 1GB: (x72, DR) 184-Pin DDR VLP RDIMM
Notes
16. tHZ and tLZ transitions occur in the same access time windows as valid data transi-
tions. These parameters are not referenced to a specific voltage level, but specify
when the device output is no longer driving (HZ) or begins driving (LZ).
17. The intent of the Don’t Care state after completion of the postamble is that the DQS-
driven signal should either be high, low, or high-Z and that any signal transition
within the input switching region must follow valid input requirements. If DQS transi-
tions to HIGH above VIH (DC) MIN, then it must not transition to LOW below VIH (DC)
MIN prior to tDQSH (MIN).
18. This is not a device limit. The device will operate with a negative value, but system
performance could be degraded due to bus turnaround.
19. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE com-
mand. The case shown (DQS going from High-Z to logic LOW) applies when no
WRITEs were previously in progress on the bus. If a previous WRITE was in progress,
DQS could be HIGH during this time, depending on tDQSS.
20. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the
minimum absolute value for the respective parameter. tRAS (MAX) for IDD measure-
ments is the largest multiple of tCK that meets the maximum absolute value for tRAS.
21. The refresh period is 64ms. This equates to an average refresh rate of 7.8125s. How-
ever, an AUTO REFRESH command must be asserted at least once every 70.3s; burst
refreshing or posting by the DRAM controller greater than eight refresh cycles is not
allowed.
22. The valid data window is derived by achieving other specifications: tHP (tCK/2),
tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates directly porpor-
tional with the clock duty cycle and a practical data valid window can be derived. The
clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality
curves.
23. Each byte lane has a corresponding DQS.
24. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH
during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during
standby).
25. To maintain a valid level, the transitioning edge of the input must:
a. Sustain a constant slew rate from the current AC level through to the target AC
level, VIL(AC) or VIH(AC).
b. Reach at least the target AC level.
c. After the AC target level is reached, continue to maintain at least the target DC
level, VIL(DC) or VIH(DC).
26. JEDEC specifies CK and CK# input slew rate must be ≥ 1 V/ns (2 V/ns differentially).
27. DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If
the DQ/DM/DQS slew rate is less than 0.5 V/ns, timing must be derated: 50ps must be
added to tDS and tDH for each 100 mV/ns reduction in slew rate. If slew rate exceeds 4
V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns.
28. VDD must not vary more than 4 percent if CKE is not active while any bank is active.
29. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by
the same amount.
30. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the
device CK and CK# inputs, collectively during bank active.
31. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN)
can be satisfied prior to the internal precharge command being issued.
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