378
7682C–AUTO–04/08
AT90CAN32/64/128
Notes:
1. All DC Characteristics contained in this datasheet are based on simulation and characterization of other AVR microcontrol-
lers manufactured in the same process technology. These values are preliminary values representing design targets, and
will be updated after characterization of actual silicon.
2. This assumes 50% clock duty cycle. The half period is actually the high time of the external clock, XTAL1.
3. This assumes 50% clock duty cycle. The half period is actually the low time of the external clock, XTAL1.
11
tRHDX
Data Hold After RD High
0
ns
12
tRLRH
RD Pulse Width
235
1.0 tCLCL – 15
ns
13
tDVWL
Data Setup to WR Low
105
0.5 tCLCL – 20
ns
14
tWHDX
Data Hold After WR High
235
1.0 tCLCL – 15
ns
15
tDVWH
Data Valid to WR High
250
1.0 tCLCL
ns
16
tWLWH
WR Pulse Width
235
1.0 tCLCL – 15
ns
Table 27-11. External Data Memory Characteristics, VCC = 2.7 - 5.5 Volts, No Wait-state (Continued)
(1)
Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min.
Max.
Min.
Max.
Table 27-12. External Data Memory Characteristics, VCC = 2.7 - 5.5 Volts, SRWn1 = 0, SRWn0 = 1 Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min.
Max.
Min.
Max.
0
1/tCLCL
Oscillator Frequency
0.0
8
MHz
10
tRLDV
Read Low to Data Valid
440
2.0 tCLCL – 60
ns
12
tRLRH
RD Pulse Width
485
2.0 tCLCL – 15
ns
15
tDVWH
Data Valid to WR High
500
2.0 tCLCL
ns
16
tWLWH
WR Pulse Width
485
2.0 tCLCL – 15
ns
Table 27-13. External Data Memory Characteristics, VCC = 2.7 - 5.5 Volts, SRWn1 = 1, SRWn0 = 0
Symbol
Parameter
4 MHz Oscillator
Variable Oscillator
Unit
Min.
Max.
Min.
Max.
0
1/tCLCL
Oscillator Frequency
0.0
8
MHz
10
tRLDV
Read Low to Data Valid
690
3.0 tCLCL – 60
ns
12
tRLRH
RD Pulse Width
735
3.0 tCLCL – 15
ns
15
tDVWH
Data Valid to WR High
750
3.0 tCLCL
ns
16
tWLWH
WR Pulse Width
735
3.0 tCLCL – 15
ns