370
7682C–AUTO–04/08
AT90CAN32/64/128
27.5
Two-wire Serial Interface Characteristics
Table 27-3 describes the requirements for devices connected to the Two-wire Serial Bus. The
AT90CAN32/64/128 Two-wire Serial Interface meets or exceeds these requirements under the
noted conditions.
Notes:
1. In AT90CAN32/64/128, this parameter is characterized and not 100% tested.
Table 27-3.
Two-wire Serial Bus Requirements
Symbol
Parameter
Condition
Min
Max
Units
VIL
Input Low-voltage
– 0.5
0.3 Vcc
V
VIH
Input High-voltage
0.7 Vcc
Vcc + 0.5
V
Vhys
Hysteresis of Schmitt Trigger Inputs
–
V
VOL
Output Low-voltage
3 mA sink current
0
0.4
V
tr
Rise Time for both SDA and SCL
20 + 0.1Cb
300
ns
Output Fall Time from VIHmin to VILmax
10 pF < Cb < 400 pF
20 + 0.1Cb
250
ns
Spikes Suppressed by Input Filter
0
ns
Ii
Input Current each I/O Pin
0.1 VCC < Vi < 0.9 VCC
– 10
10
A
Ci
Capacitance for each I/O Pin
–
10
pF
fSCL
SCL Clock Frequency
fCK
SCL, 250kHz)
0
400
kHz
Rp
Value of Pull-up resistor
fSCL ≤ 100 kHz
fSCL > 100 kHz
tHD;STA
Hold Time (repeated) START Condition
fSCL ≤ 100 kHz
4.0
–
s
fSCL > 100 kHz
0.6
–
s
tLOW
Low Period of the SCL Clock
fSCL ≤ 100 kHz
4.7
–
s
fSCL > 100 kHz
1.3
–
s
tHIGH
High period of the SCL clock
fSCL ≤ 100 kHz
4.0
–
s
fSCL > 100 kHz
0.6
–
s
tSU;STA
Set-up time for a repeated START
condition
fSCL ≤ 100 kHz
4.7
–
s
fSCL > 100 kHz
0.6
–
s
tHD;DAT
Data hold time
fSCL ≤ 100 kHz
0
3.45
s
fSCL > 100 kHz
0
0.9
s
tSU;DAT
Data setup time
fSCL ≤ 100 kHz
250
–
ns
fSCL > 100 kHz
100
–
ns
tSU;STO
Setup time for STOP condition
fSCL ≤ 100 kHz
4.0
–
s
fSCL > 100 kHz
0.6
–
s
tBUF
Bus free time between a STOP and
START condition
fSCL ≤ 100 kHz
4.7
–
s
V
C C
0,4V
–
3mA
----------------------------
1000ns
C
b
-------------------
V
C C
0,4V
–
3mA
----------------------------
300ns
C
b
----------------