213
7682C–AUTO–04/08
AT90CAN32/64/128
Bits 1.0 – TWPS: TWI Prescaler Bits
These bits can be read and written, and control the bit rate prescaler.
in the equation.
18.6.4
TWI Data Register – TWDR
In Transmit mode, TWDR contains the next byte to be transmitted. In receive mode, the TWDR
contains the last byte received. It is writable while the TWI is not in the process of shifting a byte.
This occurs when the TWI interrupt flag (TWINT) is set by hardware. Note that the Data Register
cannot be initialized by the user before the first interrupt occurs. The data in TWDR remains sta-
ble as long as TWINT is set. While data is shifted out, data on the bus is simultaneously shifted
in. TWDR always contains the last byte present on the bus, except after a wake up from a sleep
mode by the TWI interrupt. In this case, the contents of TWDR is undefined. In the case of a lost
bus arbitration, no data is lost in the transition from Master to Slave. Handling of the ACK bit is
controlled automatically by the TWI logic, the CPU cannot access the ACK bit directly.
Bits 7.0 – TWD: TWI Data Register
These eight bits constitute the next data byte to be transmitted, or the latest data byte received
on the TWI Serial Bus.
18.6.5
TWI (Slave) Address Register – TWAR
Bits 7.1 – TWA: TWI (Slave) Address Register
These seven bits constitute the slave address of the TWI unit. The TWAR should be loaded with
the 7-bit slave address to which the TWI will respond when programmed as a slave transmitter
or receiver, and not needed in the master modes. In multimaster systems, TWAR must be set in
masters which can be addressed as slaves by other masters.
Bit 0 – TWGCE: TWI General Call Recognition Enable Bit
Table 18-2.
TWI Bit Rate Prescaler
TWPS1
TWPS0
Prescaler Value
0
1
0
1
4
1
0
16
1
64
Bit
7
6
5
4
3
2
1
0
TWD7
TWD6
TWD5
TWD4
TWD3
TWD2
TWD1
TWD0
TWDR
Read/Write
R/W
Initial Value
1
Bit
7
6
5
4
3
2
1
0
TWA6
TWA5
TWA4
TWA3
TWA2
TWA1
TWA0
TWGCE
TWAR
Read/Write
R/W
Initial Value
1
0