參數(shù)資料
型號(hào)： MPC8313E-RDBC
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 6/99頁(yè)
文件大小： 0K
描述： BOARD CPU 8313E VER 2.2
標(biāo)準(zhǔn)包裝： 1
系列： PowerQUICC II™ PRO
類型： MPU
適用于相關(guān)產(chǎn)品： MPC8313E
所含物品： 板
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
14
Freescale Semiconductor
5.2
RESET AC Electrical Characteristics
This table provides the reset initialization AC timing specifications.
This table provides the PLL lock times.
6
DDR and DDR2 SDRAM
This section describes the DC and AC electrical specifications for the DDR SDRAM interface. Note that
DDR SDRAM is GVDD(typ) = 2.5 V and DDR2 SDRAM is GVDD(typ) = 1.8 V.
Table 10. RESET Initialization Timing Specifications
Parameter/Condition
Min
Max
Unit
Note
Required assertion time of HRESET or SRESET (input) to activate reset flow
32
—
tPCI_SYNC_IN
1
Required assertion time of PORESET with stable clock and power applied to
SYS_CLK_IN when the device is in PCI host mode
32
—
tSYS_CLK_IN
2
Required assertion time of PORESET with stable clock and power applied to
PCI_SYNC_IN when the device is in PCI agent mode
32
—
tPCI_SYNC_IN
1
HRESET assertion (output)
512
—
tPCI_SYNC_IN
1
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:3]
and CFG_CLK_IN_DIV) with respect to negation of PORESET when the
device is in PCI host mode
4—
tSYS_CLK_IN
2
Input setup time for POR configuration signals (CFG_RESET_SOURCE[0:2]
and CFG_CLKIN_DIV) with respect to negation of PORESET when the
device is in PCI agent mode
4—
tPCI_SYNC_IN
1
Input hold time for POR configuration signals with respect to negation of
HRESET
0—
ns
—
Time for the device to turn off POR configuration signal drivers with respect
to the assertion of HRESET
—4
ns
3
Time for the device to turn on POR configuration signal drivers with respect to
the negation of HRESET
1—
tPCI_SYNC_IN
1, 3
Notes:
1. tPCI_SYNC_IN is the clock period of the input clock applied to PCI_SYNC_IN. When the device is In PCI host mode the
primary clock is applied to the SYS_CLK_IN input, and PCI_SYNC_IN period depends on the value of CFG_CLKIN_DIV.
2. tSYS_CLK_IN is the clock period of the input clock applied to SYS_CLK_IN. It is only valid when the device is in PCI host mode.
3. POR configuration signals consists of CFG_RESET_SOURCE[0:2] and CFG_CLKIN_DIV.
Table 11. PLL Lock Times
Parameter/Condition
Min
Max
Unit
Note
PLL lock times
—
100
s—
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