參數(shù)資料
型號： MPC8313E-RDBC
廠商： Freescale Semiconductor
文件頁數(shù)： 28/99頁
文件大?。?/td> 0K
描述： BOARD CPU 8313E VER 2.2
標準包裝： 1
系列： PowerQUICC II™ PRO
類型： MPU
適用于相關(guān)產(chǎn)品： MPC8313E
所含物品： 板
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
34
Freescale Semiconductor
8.5
Ethernet Management Interface Electrical Characteristics
The electrical characteristics specified here apply to MII management interface signals MDIO
(management data input/output) and MDC (management data clock). The electrical characteristics for
MII, RMII, RGMII, SGMII, and RTBI are specified in Section 8.1, “Enhanced Three-Speed Ethernet
8.5.1
MII Management DC Electrical Characteristics
The MDC and MDIO are defined to operate at a supply voltage of 3.3 V. Table 37 provide the DC
electrical characteristics for MDIO and MDC.
TSEC_1588_CLK peak-to-peak jitter
tT1588CLKINJ
——
250
ps
Rise time eTSEC_1588_CLK
(20%–80%)
tT1588CLKINR
1.0
—
2.0
ns
Fall time eTSEC_1588_CLK
(80%–20%)
tT1588CLKINF
1.0
—
2.0
ns
TSEC_1588_CLK_OUT clock period
tT1588CLKOUT
2
t
T1588CLK
——
ns
TSEC_1588_CLK_OUT duty cycle
tT1588CLKOTH
/tT1588CLKOUT
30
50
70
%
TSEC_1588_PULSE_OUT
tT1588OV
0.5
—
3.0
ns
TSEC_1588_TRIG_IN pulse width
tT1588TRIGH
2
t
T1588CLK_MAX
——
ns
2
Notes:
1. TRX_CLK is the max clock period of eTSEC receiving clock selected by TMR_CTRL[CKSEL]. See the MPC8313E
PowerQUICC II Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers.
2. It need to be at least two times of clock period of clock selected by TMR_CTRL[CKSEL]. See the MPC8313E PowerQUICC II
Pro Integrated Processor Family Reference Manual, for a description of TMR_CTRL registers.
3. The maximum value of tT1588CLK is not only defined by the value of TRX_CLK, but also defined by the recovered clock. For
example, for 10/100/1000 Mbps modes, the maximum value of tT1588CLK is 3600, 280, and 56 ns, respectively.
Table 37. MII Management DC Electrical Characteristics When Powered at 3.3 V
Parameter
Symbol
Conditions
Min
Max
Unit
Supply voltage (3.3 V)
NVDD
—
2.97
3.63
V
Output high voltage
VOH
IOH = –1.0 mA
NVDD = Min
2.10
NVDD +0.3
V
Output low voltage
VOL
IOL = 1.0 mA
NVDD = Min
VSS
0.50
V
Input high voltage
VIH
—2.0
—
V
Input low voltage
VIL
—
0.80
V
Input high current
IIH
NVDD = Max
VIN
1 = 2.1 V
—
40
A
Input low current
IIL
NVDD = Max
VIN = 0.5 V
–600
—
A
Table 36. eTSEC IEEE 1588 AC Timing Specifications (continued)
At recommended operating conditions with L/TVDD of 3.3 V ± 5%.
Parameter/Condition
Symbol
Min
Typ
Max
Unit
Note
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