參數(shù)資料
型號: MPC8313E-RDBC
廠商: Freescale Semiconductor
文件頁數(shù): 29/99頁
文件大?。?/td> 0K
描述: BOARD CPU 8313E VER 2.2
標(biāo)準(zhǔn)包裝: 1
系列: PowerQUICC II™ PRO
類型: MPU
適用于相關(guān)產(chǎn)品: MPC8313E
所含物品:
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
35
8.5.2
MII Management AC Electrical Specifications
This table provides the MII management AC timing specifications.
This figure shows the MII management AC timing diagram.
Figure 21. MII Management Interface Timing Diagram
Note:
1. Note that the symbol VIN, in this case, represents the NVIN symbol referenced in Table 1 and Table 2.
Table 38. MII Management AC Timing Specifications
At recommended operating conditions with NVDD is 3.3 V ± 0.3V
Parameter/Condition
Symbol 1
Min
Typ
Max
Unit
Note
MDC frequency
fMDC
—2.5
MHz
2
MDC period
tMDC
—400
ns
MDC clock pulse width high
tMDCH
32
ns
MDC to MDIO delay
tMDKHDX
10
170
ns
MDIO to MDC setup time
tMDDVKH
5—
ns
MDIO to MDC hold time
tMDDXKH
0—
ns
MDC rise time
tMDCR
——
10
ns
MDC fall time
tMDHF
——
10
ns
Notes:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes
management data timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or
data hold time. Also, tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D)
reach the valid state (V) relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall
times, the latter convention is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the csb_clk speed. (The MIIMCFG[Mgmt Clock Select] field determines the clock frequency
of the Mgmt Clock EC_MDC.)
Table 37. MII Management DC Electrical Characteristics When Powered at 3.3 V (continued)
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
(Input)
(Output)
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