參數(shù)資料
型號(hào)： MPC8313E-RDBC
廠商： Freescale Semiconductor
文件頁數(shù)： 39/99頁
文件大小： 0K
描述： BOARD CPU 8313E VER 2.2
標(biāo)準(zhǔn)包裝： 1
系列： PowerQUICC II™ PRO
類型： MPU
適用于相關(guān)產(chǎn)品： MPC8313E
所含物品： 板
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
44
Freescale Semiconductor
Figure 32. Single-Ended Measurement Points for Rise and Fall Time Matching
The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol
based on application usage. Refer to the following section for detailed information:
9.2.4.1
Spread Spectrum Clock
SD_REF_CLK/SD_REF_CLK are not intended to be used with, and should not be clocked by, a spread
spectrum clock source.
9.3
SerDes Transmitter and Receiver Reference Circuits
This figure shows the reference circuits for the SerDes data lane’s transmitter and receiver.
Figure 33. SerDes Transmitter and Receiver Reference Circuits
The SerDes data lane’s DC and AC specifications are defined in the interface protocol section listed below
(SGMII) based on the application usage:
Please note that a external AC-coupling capacitor is required for the above serial transmission protocol
with the capacitor value defined in the specifications of the protocol section.
SDn_REF_CLK
VCROSS MEDIAN
VCROSS MEDIAN + 100 mV
VCROSS MEDIAN – 100 mV
TFALL
TRISE
50
Receiver
Transmitter
TXn
RXn
50
50
50
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