
11-4
MPC565/MPC566 Reference Manual
MOTOROLA
Data Memory Protection
of the access attributes are compared/matched/true, the access is directed to the U-bus by
the L2U module. If the DMPU detects an access violation, it informs the error status to the
master initiating the cycle.
When show cycles are enabled, accesses to all of the L-bus resources by the RCPU are
made visible on the U-bus side by the L2U.
The L2U is responsible for handling the effects of reservations on the L-bus and
the U-bus. For the L-bus and the U-bus, the L2U detects reservation losses and updates the
RCPU core with the reservation status.
11.4.2 Reset Operation
Upon soft reset assertion, the L2U goes to an idle state and all pending accesses are ignored.
The L2U module control registers are not initialized on the assertion of a soft reset, keeping
the system configuration unchanged.
Upon assertion of hard reset, the L2U control registers are initialized to their reset states.
While reset (hard or soft) is asserted on the U-bus, the L2U asserts the corresponding L-bus
reset signals. The L2U also drives the reset configuration word from the U-bus to the L-bus
upon assertion of hard reset.
11.4.3 Peripheral Mode
In the peripheral mode of operation the RCPU is shut down and an alternative master on
the external bus can perform accesses to any internal bus (U-bus and L-bus) slave.
The external master can also access the internal MPC500 special registers that are located
in the L2U module. In order to access one of these MPC500 registers the EMCR[CONT]
bit in the USIU must be cleared.
11.5 Data Memory Protection
The Data Memory Protection Unit (DMPU) in the L2U module provides access protection
for the memory regions on the U-bus side from load/store accesses by the RCPU. (Only
U-bus space is protected.) The DMPU does not protect MPC500 register accesses initiated
by the RCPU on the L-bus. The user can assign up to four regions of access protection
attributes and can assign global attributes to any space not included in the active regions.
When it detects an access violation, the L2U generates an exception request to the CPU. A