MOTOROLA
Chapter 10. Memory Controller
10-31
Memory Controller External Master Support
10.8 Memory Controller External Master Support
The memory controller in the MPC565/MPC566 supports accesses initiated by both
internal and external bus masters to external memories. If the address of any master is
mapped within the internal MPC565/MPC566 address space, the access will be directed to
the internal device, and will be ignored by the memory controller. If the address is not
mapped internally, but rather mapped to one of the memory controller regions, the memory
controller will provide the appropriate chip select and strobes as programmed in the
The MPC565/MPC566 supports only synchronous external bus masters. This means that
the external master works with CLKOUT and implements the MPC565/MPC566 bus
protocol to access a slave device.
A synchronous master initiates a transfer by asserting TS. The ADDR[0:31] signals must
be stable from the rising edge of CLKOUT during which TS is sampled, until the last TA
acknowledges the transfer. Since the external master works synchronously with the
MPC565/MPC566, only setup and hold times around the rising edge of CLKOUT are
important. Once the TS is detected/asserted, the memory controller compares the address
with each one of its defined valid banks to find a possible match. But, since the external
address space is shorter than the internal space, the actual address that is used for comparing
against the memory controller regions is in the format of: {00000000, bits [8:16] of the
external address}. In the case where a match is found, the controls to the memory devices
are generated and the transfer acknowledge indication (TA) is supplied to the master.
Since it takes two clocks for the external address to be recognized and handled by the
memory controller, the TS which is generated by the external master is ahead of the
corresponding CS and strobes which are asserted by the memory controller. This 2-clock
delay might cause problems in some synchronous memories. To overcome this, the
V
CS[0] = ID[3]
CS[3] = ID[20] & ID[31]
AM[0:16]
0 0000 0000 0000 0000
ATM[0:2]
000
CSNT
0
ACS[0:1]
00
EHTR
0
SCY[0:3]
0b1111
BSCY[0:2]
0b011
TRLX
0
Table 10-5. Boot Bank Fields Values After Hard Reset (continued)
Field
Value (Binary)