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MPC565/MPC566 Reference Manual
MOTOROLA
System Configuration and Protection Registers
6.14.2 SIU Interrupt Controller Registers
The SIU interrupt controller contains the following registers: SIPEND, SIPEND2 and
SIPEND3 (interrupt pending registers), SIMASK, SIMASK2 and SIMASK3 (interrupt
mask registers), SIEL, SIVEC, SISR2 and SISR3.
The SIPEND and SIMASK registers are used when the interrupt controller is configured
for regular, MPC555/MPC556 compatible, operation. SIPEND2, SIPEND3, SIMASK2,
SIMASK3, SISR2 and SISR3 registers are used only when the interrupt controller is
operating in enhanced interrupt mode.
SIPEND, SIPEND2 and SIPEND3 are 32-bit registers. Each bit in the register corresponds
to an interrupt request. The bits associated with internal exceptions indicate, if set, that an
interrupt service is requested. These bits reflect the status of the internal requesting device,
and will be cleared when the appropriate actions are initiated by software in the device
itself. Writing to these bits has no effect.
The bits associated with the IRQ pins have a different behavior depending on the sensitivity
defined for them in the SIEL register. When the IRQ is defined as a “l(fā)evel” interrupt the
corresponding bit behaves in a manner similar to the bits associated with internal interrupt
sources, (i.e., it reflects the status of the IRQ pin). This bit can not be changed by software,
it will be cleared when the external signal is negated. When the IRQ is defined as an “edge”
interrupt, if the corresponding bit is set, it indicates that a falling edge was detected on the
line. The bit must be reset by software by writing a ‘1’ to it.
The following acronym definitions apply to the various bits implemented in the SIU
interrupt controller registers.
26
CONT
Control attribute. CONT drives the internal bus control bit attribute as follows:
0 Access to MPC565/MPC566 control register, or control cycle access
1 Access to global address map
27
—
Reserved
28
TRAC
Trace attribute. TRAC controls the internal bus program trace attribute as follows:
0 Program trace
1 Not program trace
29
SIZEN
External size enable control bit. SIZEN determines how the internal bus size attribute is driven:
0 Drive size from external bus signals TSIZE[0:1]
1 Drive size from SIZE0, SIZE1 in EMCR
30:31
—
Reserved
Table 6-13. EMCR Bit Descriptions (continued)
Bit(s)
Name
Description