
MOTOROLA
Chapter 13. QADC64E Legacy Mode Operation
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Digital Subsystem
operating modes, software action is not needed between trigger events. Since both queues
Timer” for a summary of periodic/interval timer reset conditions.
Software enables the completion interrupt when using the periodic/interval timer
continuous-scan mode. When the interrupt occurs, the software knows that the periodically
collected analog results have just been taken. The software can use the periodic interrupt to
obtain non-analog inputs as well, such as contact closures, as part of a periodic look at all
inputs.
13.5.5
QADC64E Clock (QCLK) Generation
Figure 13-24 is a block diagram of the clock subsystem. The QCLK provides the timing for
the A/D converter state machine which controls the timing of the conversion. The QCLK
is also the input to a 17-stage binary divider which implements the periodic/interval timer.
To retain the specified analog conversion accuracy, the QCLK frequency (FQCLK) must be
Before using the QADC64E, the software must initialize the prescaler with values that put
the QCLK within the specified range. Though most software applications initialize the
prescaler once and do not change it, write operations to the prescaler fields are permitted.
For software compatibility with earlier versions of QADC64E, the definition of PSL, PSH,
and PSA have been maintained. However, the requirements on minimum time and
minimum low time no longer exist.
NOTE
A change in the prescaler value while a conversion is in
progress is likely to corrupt the result from any conversion in
progress. Therefore, any prescaler write operation should be
done only when both queues are in the disabled modes.