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MPC561/MPC563 Reference Manual
MOTOROLA
SCI Queue Operation
When the queue is disabled (QRE = 0), the SCI functions in single buffer receive
mode (as originally designed) and RDRF and OR function as previously defined.
Locations SCRQ[0:15] can be used as general purpose 9-bit registers. Software
should ignore all other bits pertaining to the queue.
Only data that has no errors (FE and PF both false) is allowed into the queue. The
status flags FE and PF, if set, reflect the status of data not allowed into the queue.
The receive queue is disabled until the error flags are cleared via the original SCI
mechanism and the queue is re-initialized. The pointer QRPNT indicates the queue
location where the data frame would have been stored.
Queue size capable to receive up to 16 data frames (SCRQ[0:15]) which may allow
for infinite and continuous receives.
Interrupt generation can occur when the top half (SCRQ[0:7]) of the queue has been
filled (QTHF) and the bottom half (SCRQ[8:15]) of the queue has been filled
(QBHF). This may allow for uninterrupted and continuous receives by indicating to
the CPU to start reading the queue portion that is now full.
— The QTHF bit is set by hardware when the top half is full. The QTHF bit is
cleared when the SCxSR is read with QTHF set, followed by a write of QTHF to
zero.
— The QBHF bit is set by hardware when the bottom half is full. The QBHF bit is
cleared when the SCxSR is read with QBHF set, followed by a write of QBHF
to zero.
In order to implement the receive queue, the following conditions must be met: QRE
must be set (QSCI1CR); RE must be set (SCC1R1); QOR and QTHF must be
cleared (QSCI1SR); and OR, PF, and FE must be cleared (SC1SR).
Enable and disable options for the interrupts QTHF and QBHF as controlled by the
QTHFI and QBHFI, respectfully.
4-bit counter (QRPNT) is used as a pointer to indicate where the next valid data
frame will be stored.
A queue overrun error flag (QOR) to indicate when the queue is already full when
another data frame is ready to be stored into the queue (similar to the OR bit in single
buffer mode). The QOR bit can be set for QTHF = 1 or QBHF = 1, depending on
where the store is being attempted.
The queue can be exited when an idle line is used to indicate when a group of serial
transmissions is finished. This can be achieved by using the ILIE bit to enable the
interrupt when the IDLE flag is set. The CPU can then clear QRE and/or RE
allowing the receiver queue to be exited.
For receiver queue operation, IDLE is cleared when SC1SR is read with IDLE set,
followed by a read of SCRQ[0:15].