參數(shù)資料
型號(hào): MMDF2C02E
廠商: ON SEMICONDUCTOR
英文描述: Dual Power MOSFET 2.5 Amps, 25 Volts(2.5A,25V,雙功率MOS場(chǎng)效應(yīng)管(N溝道+P溝道))
中文描述: 雙功率MOSFET2.5安培,25伏(包2.5a,25V的,雙功率馬鞍山場(chǎng)效應(yīng)管(不適用溝道P溝道))
文件頁(yè)數(shù): 6/12頁(yè)
文件大?。?/td> 140K
代理商: MMDF2C02E
MMDF2C02E
http://onsemi.com
6
TYPICAL ELECTRICAL CHARACTERISTICS
N–Channel
P–Channel
Figure 6. Drain–to–Source Leakage Current
versus Voltage
Figure 6. Drain–to–Source Leakage Current
versus Voltage
1
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
I
100
10
0
4
8
12
16
VGS = 0 V
TJ = 125
°
C
100
°
C
I
1
100
VDS, DRAIN-TO-SOURCE VOLTAGE (VOLTS)
10
5
10
15
20
VGS = 0 V
TJ = 125
°
C
100
°
C
1000
10000
25
°
C
25
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (
t)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The published capacitance data is difficult to use for
calculating rise and fall because drain–gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (IG(AV)) can be made from a
rudimentary analysis of the drive circuit so that
t = Q/IG(AV)
During the rise and fall time interval when switching a
resistive load, VGS remains virtually constant at a level
known as the plateau voltage, VSGP. Therefore, rise and fall
times may be approximated by the following:
tr = Q2 x RG/(VGG – VGSP)
tf = Q2 x RG/VGSP
where
VGG = the gate drive voltage, which varies from zero to VGG
RG = the gate drive resistance
and Q2 and VGSP are read from the gate charge curve.
During the turn–on and turn–off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
td(on) = RG Ciss In [VGG/(VGG – VGSP)]
td(off) = RG Ciss In (VGG/VGSP)
The capacitance (Ciss) is read from the capacitance curve at
a voltage corresponding to the off–state condition when
calculating td(on) and is read at a voltage corresponding to the
on–state when calculating td(off).
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
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