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參數(shù)資料
| 型號： | ML86V8208 |
| 廠商： | OKI ELECTRIC INDUSTRY CO LTD |
| 元件分類： | 顯示控制器 |
| 英文描述： | 854 X 480 PIXELS DOT MAT LCD DSPL CTLR, PQFP176 |
| 封裝： | 24 X 24 MM, 0.50 MM PITCH, PLASTIC, LQFP-176 |
| 文件頁數(shù)： | 3/31頁 |
| 文件大?。?/td> | 299K |
| 代理商： | ML86V8208 |
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PEDL86V8208-02
OKI Semiconductor
MSL86V8208
11/31
DESCRIPTION OF FUNCTIONS
Analog Video Input
The ML86V8208 has 8-port analog video input pins. These input ports can be allocated to the composite video
input, S-video input, or component video input by the setting of the control register.
The ports can also be used as selectors for multiple video inputs. (Only the selected input port is valid.)
Valid port
Input
selection
Input mode
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
VIN8
0
Composite 1
CVBS
—
1
Composite 2
—
CVBS
—
2
Composite 3
—
CVBS
—
3
Composite 4
—
CVBS
—
4
S-video 1
—
Y
—
C
—
5
S-video 2
—
Y
—
C
—
6
S-video 3
—
Y
—
C
—
7
Component YCbCr
—
Y
—
Cb
Cr
8
Component RGB
—
G
—
B
R
Others
Analog input sleep
—
Note: CVBS = Composite video signal, Y = luminance signal, C = Composite chrominance signal, Others: Each
component signal
Analog input supports composite or S-video signals specified by the ITU-R BT.470 (some are not supported) and
component signals (interlace scan only) that are specified by the SMPTE / EBU-N10.
In the case of the S-video input and component input, a composite sync signal is mixed on the Y or G signal.
Analog video signals are input by capacity coupling. The built-in clamp circuit detects the sync pulse level, and
regenerates DC level (Sync Tip clamp).
The analog signal that has been clamped is sampled by the built-in ADC. The sampling frequency is twice the
pixel clock. Three built-in ADC units are available and one, two, or three units operate simultaneously according
to the selected input video signal type. In this case, unused ADC units are set to the sleep mode to reduce power
consumption.
The following two sampling modes are available.
(1) Asynchronous sampling mode
This sampling mode uses a fixed clock.
The sampling clock is either directly input from the external pin (PLL not used) or generated from the external
reference clock using the built-in PLL. In the latter case, the sampling clock is generated with fixed divide ratio
by using 25MHz or 32MHz as an external reference clock. In both cases, the clock phase is adjusted internally
for each line since the operation is performed asynchronously with the video signal input.
This mode has an advantage of higher synchronous tracking performance for distorted synchronous signals
such as non-standard video signals. However, for the composite video input and S-video input, a large
deviation from the specified clock frequency slightly affects the color separation performance.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ML86V8208TCZ03A | 制造商:ROHM Semiconductor 功能描述:DECONV : DECODER (3CH) + SCALE |
| ML86V8208TPZ03A-7 | 制造商:ROHM Semiconductor 功能描述: |
| ML86V8208TPZ30A-7 | 制造商:ROHM Semiconductor 功能描述: |
| ML86V8209TCZ03A | 制造商:ROHM Semiconductor 功能描述: |
| ML86V8209TCZ03A-7 | 制造商:ROHM Semiconductor 功能描述:LCD CONTROLLER WITH VIDEO DECO |
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