參數(shù)資料
型號(hào)： MK68564
廠商： 意法半導(dǎo)體
英文描述： Serial Input Output(串行I/O(雙通道,多功能外圍電路))
中文描述： 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路））
文件頁數(shù)： 38/46頁
文件大?。?/td> 464K
代理商： MK68564
AC ELECTRICAL CHARACTERISTICS
(continued)
(V
CC
= 5.0 VDC
±
5%, GND = 0 VDC, T
A
= 0 to 70
°
C)
4.0 MHz
Min.
5.0 MHz
Min.
Number
Parameter
Max.
120
Max.
90
Unit
Notes
40
41
42
43
44
CS HIGH TO DATA Out High Impedence
CS or IACK High to CLK Low
TxRDY or RxRDY Width Low
CLK High TxRDY or RxRDY Low
CLK High to TxRDY or RxRDY High
IACK High to CS Low or CS High to IACK Low
(not shown)
CTS, DCD, SYNC Pulse Width High
CTS, DCD, SYNC Pulse Width Low
TxC Period
TxC Width Low
TxC Width High
TxC Low to TxD Delay (X1 Mode)
TxC Low to INTR Low Delay
RxC Period
RxC Width Low
RxC Width High
RxD to RxC High Setup Time (X1 mode)
RxC High to RxD Hold Time (X1 mode)
RxC High to INTR Low Delay
RxC High to SYNC Low Delay (output modes)
RESET Low
XTAL 1 Width High (TTL in)
XTAL 1 Width Low (TTL in)
XTAL 1 Period (TTL in)
XTAL 1 Period (crystal in)
ns
ns
100
100
7
3
3
CLK’s
ns
ns
ns
8, 10
300
300
300
300
50
50
1
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
200
200
1000
180
180
200
200
800
180
180
ns
ns
ns
ns
ns
ns
DC
DC
DC
300
9
DC
DC
DC
DC
DC
DC
300
9
DC
DC
DC
9
5
5
CLK’s
ns
ns
ns
ns
ns
CLK’s
CLK’s
CLK
ns
ns
ns
ns
10
9
1000
180
180
0
140
10
4
1
100
100
250
250
800
180
180
0
140
10
4
1
80
80
200
200
13
7
13
7
10
10
10
2000
1000
2000
1000
Notes :
1. This specification only applies if the SIO has completed all operations initiated by the previous bus cycle, when CS
or IACK was asserted. Following a read, write, or interrupt acknoledge cycle, all operations are complete within two
CLK cycles after the rising edge of CS or IACK. If CS or IACK is asserted prior to the completion of the internal
operations, the new bus cycle will be postponed.
2. If IEI meets the setup time to the falling edge of CLK, 1 1/2 cycles following the clocking in of IACK.
3. No internal interrupt request pending at the start of an interrupt acknoledge cycle.
4. Time starts when first signal goes invalid (high).
5. If an internal interrupt is pending at the end of the interrupt acknoledge cycle.
6. If Note 2 timing is not met.
7. If this spec is met, the delay listed in Note 1 will be one CLK cycle instead of two.
8. Ready signals will be negated asynchronous to the CLK, if the condition causing the assertion of the signals is
cleared.
9. If RxC and TxC are asynchronous to the System Clock, the maximum clock rate into RxC and TxC should be no
more than one-fifth the System Clock rate. If RxC and TxC are synchronized to the falling edge of the System
Clock, the maximum clock rate into RxC and TxC can be one-fourth the System Clock rate.
10. System Clock.
11. Due to the dynamic nature of the internal data bus, if CS is held low for more than a few hundred milliseconds the
MK68564
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