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參數(shù)資料
| 型號(hào)： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁(yè)數(shù)： | 1/46頁(yè) |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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MK68564
January1989
SERIAL INPUT OUTPUT
.
COMPATIBLE WITH MK68000 CPU
.
COMPATIBLE WITH MK68000 SERIES DMA’s
.
TWO INDEPENDENT FULL-DUPLEX CHAN-
NELS
.
TWO INDEPENDENT BAUD-RATE GENER-
ATORS
-
Crystal oscillator input
-
Single-phase TTL clock input
.
DIRECTLYADDRESSABLE REGISTERS
(all control registers are read/write)
.
DATA RATE IN SYNCHRONOUS OR ASYN-
CHRONOUSMODES
-
0-1.25M bits/second with 5.0MHz system
clock rate
.
SELF-TEST CAPABILITY
.
RECEIVE DATA REGISTERS ARE QUADRU-
PLY BUFFERED ; TRANSMIT REGISTERS
ARE DOUBLY BUFFERED
.
DAISY-CHAIN PRIORITY INTERRUPT LOGIC
PROVIDESAUTOMATIC INTERRUPTVECTO-
RING WITHOUT EXTERNAL LOGIC
.
MODEMSTATUSCAN BE MONITORED
-
Separate modem controls for each channel
.
ASYNCHRONOUS FEATURES
-
5, 6, 7, or 8 bits/character
-
1, 1
1/2
, or 2 stop bits
-
Even, odd, or no parity
-
x1, x16, x32, and x64 clockmodes
-
Break generation and detection
-
Parity, overrun, and framingerror detection
.
BYTE SYNCHRONOUSFEATURES
-
Internal orexternal character synchronization
-
Oneortwosync characters inseparate regis-
ters
-
Automatic sync character insertion
-
CDC-16 or CRC-CCITT block check genera-
tion and checking
.
BIT SYNCHRONOUSFEATURES
-
Abort sequence generation and detection
-
Automatic zeroinsertion and deletion
-
Automatic flaginsertion between messages
-
Address field recognition
-
I-field residue handling
-
Validreceive messages protected from over-
run
-
CRC-16 or CRC-CCITT block check genera-
tion and checking
DESCRIPTION
The MK68564 SIO (Serial Input Output) is a dual-
channel, multi-function peripheral circuit, designed
to satisfy a wide variety of serial data communica-
tions requirements in microcomputer systems. Its
basicfunction isa serial-to-parallel, parallel-to-serial
converter/controller ; however within that role, it is
systemssoftware configurable sothat its ”persona-
lity” may be optimized for any given serial data
communications application.
The MK68564 iscapable of handling asynchronous
protocols, synchronous byte-oriented protocols
(suchas IBMBisync), and synchronous bit-oriented
protocols (such asHDLC and IBM SDLC). This ver-
satile device can also be used to support virtually
any serial protocol for applications other than data
communications (cassette or floppy disk interface,
for example).
The MK68564 can generate and check CRC codes
inanysynchronous mode andmaybe programmed
to checkdata integrity invarious modes. The device
also has facilities for modem controls in each chan-
nel. In applications where these controls are not
needed,the modemcontrols may be used forgene-
ral-purpose I/O.
PDIP48
(Plastic Package)
PLCC52
(Chip Carrier)
1
1/46
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| MK68564N-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564N-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-04 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68564Q-05 | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:SERIAL INPUT OUTPUT |
| MK68590P | 制造商:STMicroelectronics 功能描述: |
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