參數(shù)資料
型號(hào)： MK68564
廠商： 意法半導(dǎo)體
英文描述： Serial Input Output(串行I/O(雙通道,多功能外圍電路))
中文描述： 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路））
文件頁(yè)數(shù)： 30/46頁(yè)
文件大?。?/td> 464K
代理商： MK68564
terminated, oratthe beginning of CRCtransmission
when the Transmit Underrun/EOM latch in Status
Register0becomes set.Whenthisbitiszero,noEx-
ternal/Status interrupts will occur.
If this bit is set when an External/Status condition is
pending, an interrupt will be requested. It is re-
commended thata ResetExternal/Status Interrupts
command (Command 2 in theCommand Register)
be issued prior to enabling External/Status inter-
rupts.
SYNC WORD REGISTER 1 (SYNC 1)
This register is programmed to contain the transmit
synccharacter inthe Monosync mode, thefirsteight
bits of the 16-bit synccharacter inthe Bysincmode,
or the transmit sync character in the External Sync
mode. This register is not used in Asynchronous
mode. In the SDLC mode, this register is program-
med to contain the secondary address field used to
compare against the address field of the SDLC
frame.The SIO does not automatically transmit the
station address at the beginning of a response
frame. This register is reset to ”00H” by a channel
or hardware reset.
SYNC WORD REGISTER 2 (SYNC 2)
This register is programmed to contain the receive
synccharacter inthe Monosyncmode,the lasteight
bits of the 16-bit synccharacter inthe Bisync mode,
or a flag character (01111110) in the SDLC mode.
This register is notused in the External Sync mode
and the Asynchronous mode. This register is reset
to ”00H” by a channel or hardware reset.
RECEIVER CONTROL REGISTER
(RCVCTL)
This register contains the control bits and parame-
ters for the receiver logic. This register is reset to
”00H” by a channel or hardware reset.
D7, D6 : Receiver Bits/Character 1 and 0
The state of these two bits determines the number
of bits to be assembled as a character in the recei-
vedserialdatastream. IfParity is enabled, one ad-
ditionalbitwillbeaddedtoeachcharacter. The num-
ber of bits per character can be changed while a
character is being assembled but only before the
number ofbits currently programmed isreached. All
data is right-justified in the shift register and trans-
ferredto the receive data FIFOin 8-bit groups.
In Asynchronous mode, transfers are made atchar-
acter boundaries, and all unused bits of character
are set to a one. In Synchronous modes and SDLC
mode, an 8-bit segment of the serial data stream is
transferred to thedata FIFOwhenthe internalcoun-
ter reaches the number of bits per character pro-
grammed. For less than eight bits per character, no
parity, the MSB bit(s) of the first transfer will be the
LSB bit(s) of thenext transfer.
D5 : Receiver Auto Enables
When this bit is set to a one, and theReceiver Ena-
ble bit is also set, a Low on the DCD input pin be-
comes the enable for the receiver. When this bit is
zero, the DCD pin is simplyaninput to theSIO,and
its status is displayed in Status Register 0.
D4 : Enter Hunt Mode
Thisbit, when written to a one, rearms the receiver
synchronization logic and forces thecomparison of
the received bit stream to the ontents of Sync Word
Register 1and/or Sync WordRegister 2, depending
upon which Synchronous modeis selected, until bit
synchronization is achieved. The SIO automatically
enters the Hunt mode after a channel or hardware
reset, after an Abort condition isdetected, or when
the receiver is disabled. Whenthe Huntmode is en-
tered, the Hunt/Sync bit in Status Register 0 is set
to a one. When synchronization is achieved, the
Hunt/Sync bitisresettoa zero.IfExternal/Status in-
terrupts are enabled, an interrupt request willbe ge-
nerated onbothtransitions of the Hunt/Syncbit.En-
ter Hunt Mode has no affect in Asynchronous
modes. Thisbitisnotlatchedandwillalwaysberead
as a zero.
D7
SYNC/
SDLC7
D6
SYNC/
SDLC6
D5
SYNC/
SDLC5
D4
SYNC/
SDLC4
D3
SYNC/
SDLC3
D2
SYNC/
SDLC2
D1
SYNC/
SDLC1
D0
SYNC/
SDLC0
D7
SYNC/
SDLC
15
D6
SYNC/
SDLC
14
D5
SYNC/
SDLC
13
D4
SYNC/
SDLC
12
D3
SYNC/
SDLC
11
D2
SYNC/
SDLC
10
D1
SYNC/
SDLC
9
D0
SYNC/
SDLC 8
RX BITS
CHAR 1
0
0
1
1
RX BITS
CHAR 0
0
1
0
1
Bits/character
(no parity)
5
6
7
8
Bits/character
(parity)
6
7
8
9
D7
D6
D5
D4
D3
D2
D1
D0
RX BITS
CHAR 1
RX BITS
CHAR 0
RX AUTO
ENAB.
HUNT
MODE
RX CRC
ENAB.
ADDR.
SEARCH
STRIP
SYNC
RX
ENABLE
MK68564
30/46
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