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參數(shù)資料
| 型號： | MK68564 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | Serial Input Output(串行I/O(雙通道,多功能外圍電路)) |
| 中文描述： | 串行輸入輸出（串行的I / O（雙通道，多功能外圍電路）） |
| 文件頁數(shù)： | 21/46頁 |
| 文件大?。?/td> | 464K |
| 代理商： | MK68564 |
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receive data streamthat match the byte loaded into
Sync Word Register 1 willbe inhibited fromloading
into the receive data FIFO. The comparison be-
tween Sync Word Register 1 and the incoming data
occursata character boundary time. This is an8-bit
comparison, regardless ofthebitspercharacterpro-
grammed. CRCcalculations willbe performed on all
bytes, even if the characters are not transferred to
the receive data FIFO, as long as the Rx CRC En-
able bit is set.
Data Transfer and Status Monitiring
. After char-
acter synchronization is achieved, the assembled
characters aretransferred to the receive data FIFO,
and the status information for each character is
transferred to thereceive error FIFO. The following
fourmodes areavailable totransferthereceived da-
ta and its associated status to theCPU.
NoReceiveInterrupts Enabled
.Thismodeisused
eitherfor polling operations orforoff-line conditions.
When transferring data, using a polling routine, the
Rx Character Available bit in Status Register 0
should becheckedtodetermine ifa receive charac-
ter is available for transfer. Only when a character
isavailableshould the receive bufferand StatusRe-
gister 1 be read. The Rx Character Available bit is
set when a character is loaded to the top of the re-
ceivedataFIFO.This bitisresetduring aread ofthe
receive buffer.
Interrupt On First Character Only
. This interrupt
mode is normally used to start a DMA transfer rou-
tine or, in some cases, a polling loop. The SIO will
generate an interrupt thefirsttimeacharacter isshif-
ted to the top of the receive data FIFO after this
modeis selected or reinitialized. An interrupt will be
generated thereafter only if a Special Receive
Condition is detected. This modeisreinitialized with
the Enable Interrupt On Next Receive Character
command. Parity Errors do not cause interrupts in
this mode ; however, a Receive Overrun Error will.
InterruptOnEvery Character
. Thisinterrupt mode
willgenerate aReceiver Interrupt every timea char-
acter is shifted to the top of the receive data FIFO.
A Special Receive Condition interrupt onaparity er-
ror is optional in this mode.
Special Receive ConditionInterrupt
. The special
condition interrupt modeis not aninterrupt mode as
such, but works in conjunction with Interrupt On E-
very Character or Interrupt On First Character Only
modes. When the StatusAffects Vector bit in either
channel is set, a Special Receive condition willmo-
dify the Receive Interrupt vector to signal the CPU
of the special condition. Receive Overrun Error and
ParityErrorare the onlySpecial Receive Conditions
in Synchronous receive mode.The overrun and pa-
rity error status bits in Status Register 1 are latched
when they occur ; they will remain latched until an
Error Reset command is issued. As long as either
one of these bitsis set,a Special ReceiveCondition
Interrupt will be generated at every character avai-
lable time. Since these two status bits are latched,
the error statusinStatus Register 1, when read, will
reflectan error inthecurrent wordinthereceivebuff-
er, in addition to any Parity or Overrun errors recei-
ved since the last Error Reset command.
CRCErrorCheckingand Receiver Message Ter-
mination
. A CRC error check on the received
message can be performed on a per character
basis under program control. The Rx CRC En-
able bit must set/reset by the program before
the next character is transferred from the receive
shift register to the receive data FIFO.This ensures
proper inclusion or exclusion of data characters in
the CRC check.
Thereisan 8-bitdelaybetween thetimeacharacter
is transferred to thereceive data FIFO and the time
thesamecharacter startstoentertheCRCchecker.
Anadditional 8-bittimesareneeded toperformCRC
calculations on the character. Due to this serial na-
ture of CRC calculations, the Receive Clock (RxC)
mustcycle16timesafter thesecond CRCcharacter
has been loaded into the receive data FIFO or
20 times (the previous 16 plus 3-bit buffer delay
and 1-bit input delay) after the last bit is at the
RxD input, before CRC calculation is complete.
The CRC Framing Error bit in Status Register 1
will contain the comparison results of the CRC
checker. The comparison results should bezero,
indicating error-free transmission. The results in the
status bit are valid only at the end of CRC cal-
culation. If the result is examined before this time, it
usually indicates an error (the bit is High). The
comparison is made at each character available
time and is valid until the character is read from the
receive data FIFO.
SDLC/HDLC OPERATION
INTRODUCTION
TheMK68564 SIOiscapable ofhandling bothHigh-
level Synchronous Data Link Control (HDLC) and
IBM Synchronous Data Link Control (SDLC)proto-
cols. In the following discussion, only SDLC is ref-
erenced because of the high degree of similarity
between SDLCand HDLC.
The SDLC mode is considerably different from
Monosync and Bisync protocols, because it is bit o-
riented rather than character oriented. Bit orienta-
tionmakesSDLCa flexibleprotocolintermsofmes-
MK68564
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